NDLI: Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough

Content Provider	ACM Digital Library
Author	Wang, Jia Agrawal, Dheeraj Dong, Qunfeng Banerjee, Suman
Abstract	Packet classification is the foundation of many Internet functions such as QoS and security. A long thread of research has proposed efficient software-based solutions to this problem. Such software solutions are attractive because they require cheap memory systems for implementation, thus bringing down the overall cost of the system. In contrast, hardware-based solutions use more expensive memory systems, e.g., TCAMs, but are often preferred by router vendors for their faster classification speeds. The goal of this paper is to find a "best-of-both-worlds" solution -- a solution that incurs the cost of a software-based system and has the speed of a hardware-based one. Our proposed solution, called smart rule cache achieves this goal by using minimal hardware -- a few additional registers -- to cache evolving rules which preserve classification semantics, and additional logic to match incoming packets to these rules. Using real traffic traces and real rule sets from a tier-1 ISP, we show such a setup is sufficient to achieve very high hit ratios for fast classification in hardware. Cache miss ratios are 2 ∼ 4 orders of magnitude lower than flow cache schemes. Given its low cost and good performance, we believe our solution may create significant impact on current industry practice.
Starting Page	253
Ending Page	264
Page Count	12
File Format	PDF
ISSN	01635999
DOI	10.1145/1269899.1254914
Journal	ACM SIGMETRICS Performance Evaluation Review (PERV)
Volume Number	35
Issue Number	1
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-01-10
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Rule evolution Rule cache Packet classification
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough

Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough.

Wire Speed Packet Classification Without TCAMs: A Few More Registers (And A Bit of Logic) Are Enough

Wire speed packet classification without tcam: one more register (and a bit of logic) is enough.

Bit weaving: a non-prefix approach to compressing packet classifiers in TCAMs

Bit Weaving: A Non-Prefix Approach to Compressing Packet Classifiers in TCAMs

A smart pre-classifier to reduce power consumption of TCAMs for multi-dimensional packet classification

Replication free rule grouping for packet classification

Wire-Speed TCAM-Based Architectures for Multimatch Packet Classification (2009)

Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough

Similar Documents

Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough

Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough.

Wire Speed Packet Classification Without TCAMs: A Few More Registers (And A Bit of Logic) Are Enough

Wire speed packet classification without tcam: one more register (and a bit of logic) is enough.

Bit weaving: a non-prefix approach to compressing packet classifiers in TCAMs

Bit Weaving: A Non-Prefix Approach to Compressing Packet Classifiers in TCAMs

A smart pre-classifier to reduce power consumption of TCAMs for multi-dimensional packet classification

Replication free rule grouping for packet classification

Wire-Speed TCAM-Based Architectures for Multimatch Packet Classification (2009)

Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough