NDLI: Modeling and improving data cache reliability:1

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Modeling and improving data cache reliability

Facilitating focused internet measurements

Two-phase routing, scheduling and power control for wireless mesh networks with variable traffic

Scalability of fork/join queueing networks with blocking

Managing energy-performance tradeoffs for multithreaded applications on multiprocessor architectures

Optimal capacity planning in stochastic loss networks with time-varying workloads

Future directions in performance evaluation research

Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough

Clustering and sharing incentives in BitTorrent systems

Evaluating SIP server performance

Diagnosing network disruptions with network-wide analysis

A machine learning approach to TCP throughput prediction

Optimizing system configurations quickly by guessing at the performance

An algorithm for approximate counting using limited memory resources

Adaptive and scalable comparison scheduling

Flow-level stability of data networks with non-convex and time-varying rate regions

Data layouts for object-oriented programs

Distributed link scheduling with constant overhead

Pipeline spectroscopy

QoS policies and architecture for cache/memory in CMP platforms

Understanding network delay changes caused by routing events

Sensitivity of PCA for traffic anomaly detection

Sizing sketches

Synthetic designs

Building high accuracy bloom filters using partitioned hashing

Theoretical bounds on control-plane self-monitoring in routing protocols

Bottom-k sketches

Modeling the relative fitness of storage

Backbone construction in selfish wireless networks

An analysis of latent sector errors in disk drives

Oblivious routing for fat-tree based system area networks with uncertain traffic demands

GRE encapsulated multicast probing

When is service really denied?

Does internet media traffic really follow Zipf-like distribution?

Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium® architecture

Power reduction through measurement and modeling of users and CPUs

Generating representative ISP topologies from first-principles

Bounding damage from link destruction, with application to the internet

Semi-supervised network traffic classification

Efficient management of idleness in systems

Asynchronous iterative solution for state-based performance metrics

Analyzing commercial processor performance numbers for predicting performance of applications of interest

Mean delay optimization for the M/G/1 queue with pareto type service times

Modeling and improving data cache reliability:1

Content Provider	ACM Digital Library
Author	Kadayif, Ismail Kandemir, Mahmut
Abstract	Soft errors arising from energetic particle strikes pose a significant reliability concern for computing systems, especially for those running in noisy environments. Technology scaling and aggressive leakage control mechanisms make the problem caused by these transient errors even more severe. Therefore, it is very important to employ reliability enhancing mechanisms in processor/memory designs to protect them against soft errors. To do so, we first need to model soft errors, and then study cost/reliability tradeoffs among various reliability enhancing techniques based on the model so that system requirements could be met. Since cache memories take the largest fraction of on-chip real estate today and their share is expected to continue to grow in future designs, they are more vulnerable to soft errors, as compared to many other components of a computing system. In this paper, we first focus on a soft error model for L1 data caches, and then explore different reliability enhancing mechanisms. More specifically, we define a metric called AVFC (Architectural Vulnerability Factor for Caches), which represents the probability with which a fault in the cache can be visible in the final output of the program. Based on this model, we then propose three architectural schemes for improving reliability in the existence of soft errors. Our first scheme prevents an error from propagating to the lower levels in the memory hierarchy by not forwarding the unmodified data words of a dirty cache block to the L2 cache when the dirty block is to be replaced. The second scheme proposed selectively invalidates cache blocks to reduce their vulnerable periods, decreasing their chances of catching any soft errors. Based on the AVFC metric, our experimental results show that these two schemes are very effective in alleviating soft errors in the L1 data cache. Specifically, by using our first scheme, it is possible to improve the AVFC metric by 32% without any performance loss. On the other hand, the second scheme enhances the AVFC metric between 60% and 97%, at the cost of a performance degradation which varies from 0% to 21.3%, depending on how aggressively the cache blocks are invalidated. To reduce the performance overhead caused by cache block invalidation, we also propose a third scheme which tries to bring a fresh copy of the invalidated block into the cache via prefetching. Our experimental results indicate that, this scheme can reduce the performance overheads to less than 1% for all applications in our experimental suite, at the cost of giving up a tolerable portion of the reliability enhancement the second scheme achieves.
File Format	PDF
ISSN	01635999
DOI	10.1145/1269899.1254884
Journal	ACM SIGMETRICS Performance Evaluation Review (PERV)
Volume Number	35
Issue Number	1
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-01-10
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Data caches Data integrity Soft errors Vulnerability factors Reliability
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture Software

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