NDLI: Energy Optimization of Subthreshold-Voltage Sensor Network Processors

Please wait, while we are loading the content...

Volume 33, Issue 5, December 2005

Volume 33, Issue 4, November 2005

Volume 33, Issue 3, June 2005

Volume 33, Issue 2, May 2005

General Chair's Message

Program Chair's Message

Architecture for Protecting Critical Secrets in Microprocessors

High Efficiency Counter Mode Security Architecture via Prediction and Precomputation

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions

Disk Drive Roadmap from the Thermal Perspective

Direct Cache Access for High Bandwidth Network I/O

Deconstructing Commodity Storage Clusters

A Robust Main-Memory Compression Scheme

Continuous Optimization

A High Throughput String Matching Architecture for Intrusion Detection and Prevention

A Tree Based Router Search Engine Architecture with Single Port Memories

An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems

Design and Evaluation of Hybrid Fault-Detection Systems

Opportunistic Transient-Fault Detection

An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures

Energy Optimization of Subthreshold-Voltage Sensor Network Processors

An Ultra Low Power System Architecture for Sensor Network Applications

Temporal Streaming of Shared Memory

Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking

Improving Program Efficiency by Packing Instructions into Registers

An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors

Mitigating Amdahl's Law through EPI Throttling

Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines

Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection

Victim Replication

Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors

Optimizing Replication, Communication, and Capacity Allocation in CMPs

Techniques for Efficient Processing in Runahead Execution Engines

Piecewise Linear Branch Prediction

Analysis of the O-GEometric History Length Branch Predictor

Interconnections in Multi-Core Architectures

Microarchitecture of a High-Radix Router

Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks

Scalable Load and Store Processing in Latency Tolerant Processors

Store Vulnerability Window (SVW)

Store Buffer Design in First-Level Multibanked Data Caches

Dynamic Verification of Sequential Consistency

Virtualizing Transactional Memory

The Impact of Performance Asymmetry in Emerging Multicore Architectures

Exploiting Structural Duplication for Lifetime Reliability Enhancement

Computing Architectural Vulnerability Factors for Address-Based Structures

The V-Way Cache

Volume 33, Issue 1, March 2005

Energy Optimization of Subthreshold-Voltage Sensor Network Processors

Content Provider	ACM Digital Library
Author	Helfand, Ryan Olson, Javin Blaauw, David Minuth, Michael Zhai, Bo Austin, Todd Nazhandali, Leyla Pant, Sanjay Reeves, Anna
Abstract	Sensor network processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performance requirement and extremely high energy constraints, such that sensor network processors must execute low-performance tasks for long durations on small energy supplies. In this paper, we demonstrate that subthreshold-voltage circuit design (400 mV and below) lends itself well to the performance and energy demands of sensor network processors. Moreover, we show that the landscape for microarchitectural energy optimization dramatically changes in the subthreshold domain. The dominance of leakage power in the subthreshold regime demands architectures that i) reduce overall area, ii) increase the utility of transistors, while iii) maintaining acceptable CPI efficiency. We confirm these observations by performing SPICE-level analysis of 21 sensor network processors and memory architectures. Our best sensor platform, implemented in 130nm CMOS and operating at 235 mV, only consumes 1.38 pJ/instruction, nearly an order of magnitude less energy than previously published sensor network processor results. This design, accompanied by bulk-silicon solar cells for energy scavenging, has been manufactured by IBM and is currently being tested.
Starting Page	197
Ending Page	207
Page Count	11
File Format	PDF
ISSN	01635964
DOI	10.1145/1080695.1069987
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	33
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in