NDLI: Exploring the cache design space for large scale CMPs

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Volume 33, Issue 5, December 2005

Volume 33, Issue 4, November 2005

Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05)

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

Internet Nuggets

Performance/Watt

The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors

Notes from HPPAC 2005

Exploring the cache design space for large scale CMPs

A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware

A chip prototyping substrate

Improving memory system performance with energy-efficient value speculation

Chip multi-processor scalability for single-threaded applications

Hardware-modulated parallelism in chip multiprocessors

Fast synchronization for chip multiprocessors

Dynamically configurable shared CMP helper engines for improved performance

Performance implications of single thread migration on a chip multi-core

Volume 33, Issue 3, June 2005

Volume 33, Issue 2, May 2005

Volume 33, Issue 1, March 2005

Exploring the cache design space for large scale CMPs

Content Provider	ACM Digital Library
Author	Hsu, Lisa Iyer, Ravi Reinhardt, Steve Newell, Donald Makineni, Srihari
Abstract	With the advent of dual-core chips in the marketplace, small-scale CMP (chip multiprocessor) architectures are becoming commonplace. We expect a continuing trend of increasing the number of cores on a die to maximize the performance/power efficiency of a single chip. We believe an era of large-scale CMPs (LCMPs) with several tens to hundreds of cores is on the way, but as of now architects have little understanding of how best to build a cache hierarchy given such a large number of cores/threads to support. With this in mind, our initial goals are to prune the cache design space for LCMPs by characterizing basic server workload behavior in such an environment.In this paper, we describe the range of methodologies that we are developing to overcome the challenges of exploring the cache design space for LCMP platforms. We then focus on employing a trace-driven approach to characterizing one key server workload (OLTP) in both a homogeneous and a heterogeneous workload environment. We study the effect of increasing threads (from 1 to 128) on a three-level cache hierarchy with emphasis on second and third level caches. We study the effect of varying sizes at these cache levels and show the effects of threads contending for cache space, the effects of prefetching instruction addresses, and the effects of inclusion. We make initial observations and conclusions about the factors on which LCMP cache hierarchy design decisions should be based and discuss future work.
Starting Page	24
Ending Page	33
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/1105734.1105739
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	33
Issue Number	4
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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