NDLI: The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors

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Volume 33, Issue 5, December 2005

Volume 33, Issue 4, November 2005

Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05)

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

Internet Nuggets

Performance/Watt

The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors

Notes from HPPAC 2005

Exploring the cache design space for large scale CMPs

A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware

A chip prototyping substrate

Improving memory system performance with energy-efficient value speculation

Chip multi-processor scalability for single-threaded applications

Hardware-modulated parallelism in chip multiprocessors

Fast synchronization for chip multiprocessors

Dynamically configurable shared CMP helper engines for improved performance

Performance implications of single thread migration on a chip multi-core

Volume 33, Issue 3, June 2005

Volume 33, Issue 2, May 2005

Volume 33, Issue 1, March 2005

The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors

Content Provider	ACM Digital Library
Author	Laudon, James Davis, John D. Fu, Cong
Abstract	We present RASE, a full system high performance simulation methodology for simulating complex server applications and server class chip multiprocessors enabled with fine-grain multithreading (CMTs). RASE combines application knowledge, operating system information, and data access patterns with an instruction stream from a highly-tuned, scalable steady-state benchmark [5] [22] to generate multiple representative instruction streams that can be mapped to a variety of CMT configurations. We use execution-driven simulation to generate instruction streams for M processors and store them as instruction trace files (several billion instructions per processor) that can be post-processed and augmented for larger than M processor system simulation. We use SPEC JBB2000, TPC-C, and an XML server benchmark to compare the performance estimates of RASE to a reference prototype CMT system. By varying M, we find that our trace-driven simulation methodology predicts within 5% of the instructions per cycle (IPC) of the reference hardware for the applications. Without post-processing the traces, in the best cases, the performance prediction accuracy degrades to 20-40% of the real IPC for instruction traces that require a high replication factor.
Starting Page	14
Ending Page	23
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/1105734.1105738
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	33
Issue Number	4
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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