NDLI: A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Content Provider	ACM Digital Library
Author	Brockman, Jay B. Monchiero, Matteo Thoziyoor, Shyamkumar Ahn, Jung Ho Jouppi, Norman P.
Abstract	In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs. We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logic process based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.
Starting Page	51
Ending Page	62
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/1394608.1382127
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	36
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Llc cacti cache sram commodity dram logic-process based dram
Content Type	Text
Resource Type	Article

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