NDLI: Enhancing software reliability with speculative threads (CARN, Vol. 30, Issue. 5)

Please wait, while we are loading the content...

Volume 30, Issue 5, December 2002

Transactional lock-free execution of lock-based programs

Automatically characterizing large scale program behavior

Design and evaluation of compiler algorithms for pre-execution

Dynamic dead-instruction detection and elimination

Increasing web server throughput with network interface data caching

A stateless, content-directed data prefetching mechanism

Keynote address: Sensor network research

Speculative synchronization

Bytecode fetch optimization for a Java interpreter

Energy-efficient computing for wildlife tracking

Compiler optimization of scalar value communication between speculative threads

An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

Programming language optimizations for modular router configurations

A stream compiler for communication-exposed architectures

Temporally silent stores

Understanding and improving operating system effects in control flow prediction

Enabling trusted software integrity

Joint local and global hardware adaptations for energy

Enhancing software reliability with speculative threads

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router

Evolving RPC for active storage

Mondrian memory protection

Volume 30, Issue 4, September 2002

Volume 30, Issue 3, June 2002

Volume 30, Issue 2, May 2002

Volume 30, Issue 1, March 2002

Enhancing software reliability with speculative threads (CARN, Vol. 30, Issue. 5)

Content Provider	ACM Digital Library
Author	Oplinger, Jeffrey Lam, Monica S.
Abstract	This paper advocates the use of a monitor-and-recover programming paradigm to enhance the reliability of software, and proposes an architectural design that allows software and hardware to cooperate in making this paradigm more efficient and easier to program.We propose that programmers write monitoring functions assuming simple sequential execution semantics. Our architecture speeds up the computation by executing the monitoring functions speculatively in parallel with the main computation. For recovery, programmers can define fine-grain transactions whose side effects, including all register modifications and memory writes, can either be committed or aborted under program control. Transactions are implemented efficiently by treating them as speculative threads.Our experimental results suggest that monitored execution is more amenable to parallelization than regular program execution. Code monitoring is sped up by a factor of 1.5 by exploiting single-thread instruction-level parallelism, and by an additional factor of 1.6 using thread-level speculation. This results in an overall improvement of 2.5 times and a sustained 5.4 instructions-per-cycle performance. A monitored execution that used to be 2.5 times slower executes with a degradation of only 12% when compared to the performance on the baseline machine. We also show that the concept of fine-grain transactional programming is useful in catching buffer overrun errors through a number of real-life examples.
Starting Page	184
Ending Page	196
Page Count	13
File Format	PDF
ISSN	01635964
DOI	10.1145/635506.605417
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	30
Issue Number	5
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in