NDLI: A real-time support processor for ada tasking

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Volume 17, Issue 2, April 1989

Architecture and compiler tradeoffs for a long instruction wordprocessor

Tradeoffs in instruction format design for horizontal architectures

Overlapped loop support in the Cydra 5

Architectural support for synchronous task communication

The fuzzy barrier: a mechanism for high speed synchronization of processors

Efficient synchronization primitives for large-scale cache-coherent multiprocessors

A software instruction counter

Efficient debugging primitives for multiprocessors

Sheaved memory: architectural support for state saving and restoration in pages systems

Reference history, page size, and migration daemons in local/remote architectures

Translation lookaside buffer consistency: a software approach

Failure correction techniques for large disk arrays

A unified vector/scalar floating-point architecture

Data buffering: run-time versus compile-time support

An analysis of 8086 instruction set usage in MS DOS programs

A real-time support processor for ada tasking

The runtime environment for Scheme, a Scheme implementation on the 88000

Program optimization for instruction caches

Using registers to optimize cross-domain call performance

The design of nectar: a network backplane for heterogeneous multicomputers

A message driven OR-parallel machine

Evaluating the performance of software cache coherence

Analysis of cache invalidation patterns in multiprocessors

The effect of sharing on the cache and bus performance of parallel programs

Available instruction-level parallelism for superscalar and superpipelined machines

Micro-optimization of floating-point operations

Limits on multiple instruction issue

Volume 17, Issue 1, March 1989

A real-time support processor for ada tasking

Content Provider	ACM Digital Library
Author	Roos, J.
Abstract	Task synchronization in Ada causes excessive run-time overhead due to the complex semantics of the rendezvous. To demonstrate that the speed can be increased by two orders of magnitude by using special purpose hardware, a single chip VLSI support processor has been designed. By providing predictable and uniformly low overhead for the entire semantics of a rendezvous, the powerful real-time constructs of Ada can be used freely without performance degradation.The key to high performance is the set of primitive operations implemented in hardware. Each operation is complex enough to replace a considerable amount of code was designed to execute with a minimum of communication overhead. Task control blocks are stored on-chip as well as headers for entry, delay and ready queues. All necessary scheduling is integrated in the operations. Delays are handled completely on-chip using an internal real-time clock.A multilevel design strategy, based on silicon compilation, made it possible to run actual Ada programs on a functional emulator of the chip and use the results to verify the detailed design. A high degree of parallelism and pipelining together with an elaborate internal addressing scheme has reduced the number of clock cycles needed to perform each operation. Using 2 μm CMOS, the processor can run at 20 MHz. A complex rendezvous, including the calling sequence and all necessary scheduling, can be performed in less than 15 μs.
Starting Page	162
Ending Page	171
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/68182.68198
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	17
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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