NDLI: A unified vector/scalar floating-point architecture

Content Provider	ACM Digital Library
Author	Wall, D. W. Jouppi, N. P. Bertoni, J.
Abstract	In this paper we present a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The goal of this architecture is to yield improved scalar performance while broadening the range of vectorizable applications. For example, reduction operations and recurrences can be expressed in vector form in this architecture. This approach results in greater overall performance for most applications than does the approach of emphasizing peak vector performance. The hardware required to support the enhanced vector capability is insignificant, but allows the execution of two operations per cycle for vectorized code. Moreover, the size of the unified vector/scalar register file required for peak performance is an order of magnitude smaller than traditional vector register files, allowing efficient on-chip VLSI implementation. The results of simulations of the Livermore Loops and Linpack using this architecture are presented.
Starting Page	134
Ending Page	143
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/68182.68195
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	17
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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A unified vector/scalar floating-point architecture