NDLI: A Write-Aware STTRAM-Based Register File Architecture for GPGPU

Please wait, while we are loading the content...

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 13

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 12

Issue 4(Regular Papers), July 2016

Issue 3(Special Issue on Cross-Layer System Design and Regular Papers), September 2015

Issue 2(Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies), August 2015

Issue 1, July 2015

mNoC: Large Nanophotonic Network-on-Chip Crossbars with Molecular Scale Devices

Multilayer Graphene Nanoribbon and Carbon Nanotube Based Floating Gate Transistor for Nonvolatile Flash Memory

A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory

Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage

MN-MATE: Elastic Resource Management of Manycores and a Hybrid Memory Hierarchy for a Cloud Node

A Write-Aware STTRAM-Based Register File Architecture for GPGPU

A Sub-μ A Stand-By Current Synchronous Electric Charge Extractor for Piezoelectric Energy Harvesting

Quick: A HW/SW Approach for Computing across Power Cycles in Transiently Powered Computers

Fault-Tolerant Operations for Universal Blind Quantum Computation

SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 11

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 10

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 9

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 8

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 7

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 6

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 5

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 4

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 3

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 2

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 1

A Write-Aware STTRAM-Based Register File Architecture for GPGPU

Content Provider	ACM Digital Library
Author	Wang, Jue Xie, Yuan
Copyright Year	2015
Abstract	The massively parallel processing capacity of GPGPUs requires a large register file (RF), and its size keeps increasing to support more concurrent threads from generation to generation. Using traditional SRAM-based RFs, there are concerns in both area cost and energy consumption, and soon they will become unrealistic. In this work, we analyze the feasibility of using STTRAM-based RF designs, which have benefits in terms of smaller silicon area and zero standby leakage power. However, STTRAM long write latency and high write energy bring new challenges. Therefore, we propose a write-aware STTRAM-based RF architecture (WarRF), which contains two techniques: Split Bank Write modifies the arbitrator design to increase the parallelism of read and write accesses in the same bank; Write Pool reduces the number of repeated write accesses to RFs. Our experiment shows that the performance of STTRAM-based RF is improved by 13% and up to 23% after adopting WarRF. In addition, the energy consumption is reduced by 38% on average compared to SRAM-based RFs.
Starting Page	1
Ending Page	12
Page Count	12
File Format	PDF
ISSN	15504832
e-ISSN	15504840
DOI	10.1145/2700230
Journal	ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number	12
Issue Number	1
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-08-03
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	GPGPU Nonvolatile memory STTRAM Register file
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file

A shift-register-based QCA memory architecture

A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA

A new hierarchical disk architecture

Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory

Using NUMA interconnects for highly available filers

A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory

A Write-Aware STTRAM-Based Register File Architecture for GPGPU

Similar Documents

Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file

A shift-register-based QCA memory architecture

A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA

A new hierarchical disk architecture

Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory

Using NUMA interconnects for highly available filers

A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory

A Write-Aware STTRAM-Based Register File Architecture for GPGPU