NDLI: Clock-Tree Synthesis with Methodology of Reuse in 3D-IC

Content Provider	ACM Digital Library
Author	Chen, Fu-Wei Hwang, Tingting
Copyright Year	2014
Abstract	IP reuse methodology has been used extensively in SoC (system-on-chip) design. In this reuse methodology, while design and implementation costs are saved, manufacturing cost is not. To further reduce the cost, this reuse concept has been proposed at mask and die level in three-dimensional integrated circuits (3D-IC). In order to achieve manufacturing reuse, in this article, we propose a new methodology for designing a global clock tree in 3D-IC. The objective is to extend an existing clock tree in 2D IC to 3D IC, taking into consideration the wirelength, clock skew, and the number of TSVs. Compared with NNG- and 3D-MMM-based methods, our proposed method reduces the wirelength of the new die and the skew of the global 3D clock tree on average, 5.85% and 2.3%, and 76.92% and 48.7%, respectively. In more than two die design, the average improvements of the wirelength and clock skew of our method as compared with the 3D-MMM-based method are 4.23% and 46.84%, respectively.
Starting Page	1
Ending Page	22
Page Count	22
File Format	PDF
ISSN	15504832
e-ISSN	15504840
DOI	10.1145/2567668
Journal	ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number	10
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-05-06
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	3D-IC Clock-tree synthesis Clock network Through-silicon-via
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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