NDLI: NBTI-aware circuit node criticality computation

Content Provider	ACM Digital Library
Author	Yang, Shengqi Wang, Wenping Hagan, Mark Zhang, Wei Gupta, Pallav Cao, Yu
Copyright Year	2013
Abstract	For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable effort on accurate modeling and characterization of circuit delay degradation caused by NBTI at different design levels. The search for techniques and methodologies which can aid in effectively minimizing the NBTI effect on circuit delay is still underway. In this work, we present the usage of node criticality computation to drive NBTI-aware timing analysis and optimization. Circuits that have undergone this optimization flow show strong resistance to NBTI delay degradation. For the first time, this work proposes a node criticality computation algorithm under an NBTI-aware timing analysis and optimization framework. Our work provides answers to the following yet unaddressed questions: (a) what is the definition of node criticality in a circuit under the NBTI effect? (b) how do we identify the critical nodes that, once protected, will be immune to NBTI timing degradation? and (c) what are the NBTI effect attenuation approaches? Experimental results indicate that by protecting the critical nodes found by our proposed methodology, circuit delay degradation can be reduced by up to 50%. Combined with peak temperature reduction, the delay degradation can be be further improved.
Starting Page	1
Ending Page	19
Page Count	19
File Format	PDF
ISSN	15504832
e-ISSN	15504840
DOI	10.1145/2491681
Journal	ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number	9
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-10-08
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Negative bias temperature instability Circuit aging and reliability Computer-aided design Node criticality computation Timing analysis and optimization
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software

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