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Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs

Content Provider	ACM Digital Library
Author	Thapliyal, Himanshu Ranganathan, Nagarajan
Copyright Year	2010
Abstract	Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.
Starting Page	1
Ending Page	31
Page Count	31
File Format	PDF
ISSN	15504832
e-ISSN	15504840
DOI	10.1145/1877745.1877748
Journal	ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number	6
Issue Number	4
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-12-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Fredkin gate Reversible logic Sequential circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software

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