NDLI: Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Please wait, while we are loading the content...

ACM Transactions on Embedded Computing Systems (TECS) : Volume 16

ACM Transactions on Embedded Computing Systems (TECS) : Volume 15

ACM Transactions on Embedded Computing Systems (TECS) : Volume 14

Issue 4, December 2015

Issue 3(Special Issue on Embedded Platforms for Crypto and Regular Papers), May 2015

Issue 2, March 2015

Editorial: Oh Security—Where Art Thou?

Stability of Online Resource Managers for Distributed Systems under Execution Time Variations

Mobile Computations with Surrounding Devices: Proximity Sensing and MultiLayered Work Stealing

Heuristics on Reachability Trees for Bicriteria Scheduling of Stream Graphs on Heterogeneous Multiprocessor Architectures

Runtime Optimization of System Utility with Variable Hardware

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Factored Planning: From Automata to Petri Nets

Automatic Update of Indoor Location Fingerprints with Pedestrian Dead Reckoning

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash

Plugging Versus Logging: Adaptive Buffer Management for Hybrid-Mapping SSDs

Temperature-Aware Data Allocation for Embedded Systems with Cache and Scratchpad Memory

Multilevel Phase Analysis

Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Towards Write-Activity-Aware Page Table Management for Non-volatile Main Memories

A Java Processor IP Design for Embedded SoC

A Hardware-Efficient Architecture for Accurate Real-Time Disparity Map Estimation

Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems

ACDC: Small, Predictable and High-Performance Data Cache

Effective Runtime Resource Management Using Linux Control Groups with the BarbequeRTRM Framework

Issue 1, January 2015

ACM Transactions on Embedded Computing Systems (TECS) : Volume 13

ACM Transactions on Embedded Computing Systems (TECS) : Volume 12

ACM Transactions on Embedded Computing Systems (TECS) : Volume 11

ACM Transactions on Embedded Computing Systems (TECS) : Volume 11S

ACM Transactions on Embedded Computing Systems (TECS) : Volume 10

ACM Transactions on Embedded Computing Systems (TECS) : Volume 9

ACM Transactions on Embedded Computing Systems (TECS) : Volume 8

ACM Transactions on Embedded Computing Systems (TECS) : Volume 7

ACM Transactions on Embedded Computing Systems (TECS) : Volume 6

ACM Transactions on Embedded Computing Systems (TECS) : Volume 5

ACM Transactions on Embedded Computing Systems (TECS) : Volume 4

ACM Transactions on Embedded Computing Systems (TECS) : Volume 3

ACM Transactions on Embedded Computing Systems (TECS) : Volume 2

ACM Transactions on Embedded Computing Systems (TECS) : Volume 1

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Content Provider	ACM Digital Library
Author	Purnaprajna, Madhura Burg, Andreas Andrade, Joao Ienne, Paolo Falcao, Gabriel Antonopoulos, Christos Karakonstantis, Georgios Owaida, Muhsen Novo, David Bellas, Nikolaos
Copyright Year	2015
Abstract	The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.
Starting Page	1
Ending Page	23
Page Count	23
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/2656207
Volume Number	14
Issue Number	2
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-02-17
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Design space exploration FPGAs GPUs OpenCL Parallel computing Simulation tools
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An OpenCL micro-benchmark suite for GPUs and CPUs

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case

GPUrpc: Exploring Transparent Access to Remote GPUs

MINIME-GPU: Multicore Benchmark Synthesizer for GPUs

The GPU Computing Era

GPUs and the Future of Parallel Computing

Automatic and Portable Mapping of Data Parallel Programs to OpenCL for GPU-Based Heterogeneous Systems

OpenCL as a unified programming model for heterogeneous CPU/GPU clusters

Box-counting algorithm on GPU and multi-core CPU: an OpenCL cross-platform study

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Similar Documents

An OpenCL micro-benchmark suite for GPUs and CPUs

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case

GPUrpc: Exploring Transparent Access to Remote GPUs

MINIME-GPU: Multicore Benchmark Synthesizer for GPUs

The GPU Computing Era

GPUs and the Future of Parallel Computing

Automatic and Portable Mapping of Data Parallel Programs to OpenCL for GPU-Based Heterogeneous Systems

OpenCL as a unified programming model for heterogeneous CPU/GPU clusters

Box-counting algorithm on GPU and multi-core CPU: an OpenCL cross-platform study

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs