NDLI: Reducing code size through address register assignment

Content Provider	ACM Digital Library
Author	Kandemir, M. Ramanujam, J. Irwin, M. J. Chen, G.
Copyright Year	2006
Abstract	In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance, since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55%). This work presents a compiler-based optimization strategy to “reduce the code size in embedded systems.” Our strategy maximizes the use of indirect addressing modes with postincrement/decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring). Experimental results on a set of benchmark codes show the effectiveness of our solution and indicate that our approach outperforms the previous approaches to the problem. In addition to resulting in significant reductions in instruction memory (storage) requirements, the proposed technique improves execution time.
Starting Page	225
Ending Page	258
Page Count	34
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/1132357.1132365
Volume Number	5
Issue Number	1
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-02-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	DSP Software compilation Address registers Register assignment
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

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