NDLI: A formal method for hardware IP design and integration under I/O and timing constraints

Content Provider	ACM Digital Library
Author	Coussy, Philippe Bomel, Pierre Martin, Eric Casseau, Emmanuel Baganne, Adel
Copyright Year	2006
Abstract	IP integration, which is one of the most important SoC design steps, requires taking into account communication and timing constraints. In that context, design and reuse can be improved using IP cores described at a high abstraction level. In this paper, we present an IP design approach that relies on three main phases: (1) constraint modeling, (2) IP constraint analysis steps for feasibility checking, and (3) synthesis. We propose a set of techniques dedicated to the digital signal processing domain that lead to an optimized IP core integration. Based on a generic architecture of components, the method we propose provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach with a DCT core design case study.
Starting Page	29
Ending Page	53
Page Count	25
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/1132357.1132359
Volume Number	5
Issue Number	1
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-02-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	IP design and integration SoC Communication interface unit Constrained synthesis Digital signal processing and multimedia applications
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

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