NDLI: Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms

Please wait, while we are loading the content...

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

Issue 1, December 2016

A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace Computing

Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization Metrics

Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip

A Flexible SoC and Its Methodology for Parser-Based Applications

A Microcoded Kernel Recursive Least Squares Processor Using FPGA Technology

Acceleration of k-Means Algorithm Using Altera SDK for OpenCL

Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System

Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms

Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms

Content Provider	ACM Digital Library
Author	Koushanfar, Farinaz Rouhani, Bita Darvish Mirhoseini, Azalia Songhori, Ebrahim M.
Copyright Year	2016
Description	Author Affiliation: UC San Diego, La Jolla, CA(Songhori, Ebrahim M.; Rice university, Houston, TX (Mirhoseini, Azalia; Koushanfar, Farinaz); Rouhani, Bita Darvish)
Abstract	We propose SSketch, a novel automated framework for efficient analysis of dynamic big data with dense (non-sparse) correlation matrices on reconfigurable platforms. SSketch targets $\textit{streaming}$ applications where each data sample can be processed only once and storage is severely limited. Our framework adaptively learns from the stream of input data and updates a corresponding ensemble of lower-dimensional data structures, a.k.a., a sketch matrix. A new sketching methodology is introduced that tailors the problem of transforming the big data with dense correlations to an ensemble of lower-dimensional subspaces such that it is suitable for hardware-based acceleration performed by reconfigurable hardware. The new method is scalable, while it significantly reduces costly memory interactions and enhances matrix computation performance by leveraging coarse-grained parallelism existing in the dataset. SSketch provides an automated optimization methodology for creating the most accurate data sketch for a given set of user-defined constraints, including runtime and power as well as platform constraints such as memory. To facilitate automation, SSketch takes advantage of a Hardware/Software (HW/SW) co-design approach: It provides an Application Programming Interface that can be customized for rapid prototyping of an arbitrary matrix-based data analysis algorithm. Proof-of-concept evaluations on a variety of visual datasets with more than 11 million non-zeros demonstrate up to a 200-fold speedup on our hardware-accelerated realization of SSketch compared to a software-based deployment on a general-purpose processor.
Starting Page	1
Ending Page	22
Page Count	22
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/2974023
Volume Number	10
Issue Number	1
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-12-19
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FPGA HW/SW co-design Streaming model Big data Dense matrix Lower dimensional embedding Matrix sketching Matrix-based analysis
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

SSketch: An Automated Framework for Streaming Sketch-Based Analysis of Big Data on FPGA

A real-time hw/sw co-design approach based on.

Real time high precision harmonic analysis of signals in power systems using HW/SW Co-Design methodology on FPGAs

A Real-Time HW/SW Co-Design Approach Based on the SIGNAL Language and its Environment

A Real-Time HW/SW Co-Design Approach Based on the SIGNAL Language and its Environment

Electrotechnical Review, Ljubljana, Slovenija HW/SW Co-design of Real-time Video Applications Using a Custom Configurable Prototyping Platform

Embedded UML: a merger of real-time UML and co-design

HW/SW Co-Design by Automatic Embedding of Complex IP Cores

Pilot — A Platform-Based HW/SW Synthesis System for FPSoC,” Workshop on Software Support for Reconfigurable Systems (2003)

Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms

Similar Documents

SSketch: An Automated Framework for Streaming Sketch-Based Analysis of Big Data on FPGA

A real-time hw/sw co-design approach based on.

Real time high precision harmonic analysis of signals in power systems using HW/SW Co-Design methodology on FPGAs

A Real-Time HW/SW Co-Design Approach Based on the SIGNAL Language and its Environment

A Real-Time HW/SW Co-Design Approach Based on the SIGNAL Language and its Environment

Electrotechnical Review, Ljubljana, Slovenija HW/SW Co-design of Real-time Video Applications Using a Custom Configurable Prototyping Platform

Embedded UML: a merger of real-time UML and co-design

HW/SW Co-Design by Automatic Embedding of Complex IP Cores

Pilot — A Platform-Based HW/SW Synthesis System for FPSoC,” Workshop on Software Support for Reconfigurable Systems (2003)

Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms