NDLI: A Microcoded Kernel Recursive Least Squares Processor Using FPGA Technology

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

Issue 1, December 2016

A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace Computing

Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization Metrics

Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip

A Flexible SoC and Its Methodology for Parser-Based Applications

A Microcoded Kernel Recursive Least Squares Processor Using FPGA Technology

Acceleration of k-Means Algorithm Using Altera SDK for OpenCL

Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System

Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms

Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

A Microcoded Kernel Recursive Least Squares Processor Using FPGA Technology

Content Provider	ACM Digital Library
Author	Wang, Shaojun Leong, Philip H. W. Peng, Yu Peng, Xiyuan Pang, Yeyong Fraser, Nicholas J.
Copyright Year	2016
Description	Author Affiliation: Harbin Institute of Technology(Leong, Philip H W; The university of sydney (fraser, Nicholas J.; Peng, Xiyuan); Peng, Yu; Wang, Shaojun; Pang, Yeyong)
Abstract	Kernel methods utilize linear methods in a nonlinear feature space and combine the advantages of both. Online kernel methods, such as kernel recursive least squares (KRLS) and kernel normalized least mean squares (KNLMS), perform nonlinear regression in a recursive manner, with similar computational requirements to linear techniques. In this article, an architecture for a microcoded kernel method accelerator is described, and high-performance implementations of sliding-window KRLS, fixed-budget KRLS, and KNLMS are presented. The architecture utilizes pipelining and vectorization for performance, and microcoding for reusability. The design can be scaled to allow tradeoffs between capacity, performance, and area. The design is compared with a central processing unit (CPU), digital signal processor (DSP), and Altera OpenCL implementations. In different configurations on an Altera Arria 10 device, our SW-KRLS implementation delivers floating-point throughput of approximately 16 GFLOPs, latency of $5.5μ\textit{S},$ and energy consumption of 10™ 4 J, these being improvements over a CPU by factors of 12, 17, and 24, respectively.
Starting Page	1
Ending Page	22
Page Count	22
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/2950061
Volume Number	10
Issue Number	1
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-09-24
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Kernel methods Field-programmable gate array (FPGA) Pipeline Vector processors
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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