NDLI: Resistive GP-SIMD Processing-In-Memory

Content Provider	ACM Digital Library
Author	Yavits, Leonid Kvatinsky, Shahar Ginosar, Ran Morad, Amir
Copyright Year	2016
Abstract	GP-SIMD, a novel hybrid general-purpose SIMD architecture, addresses the challenge of data synchronization by in-memory computing, through combining data storage and massive parallel processing. In this article, we explore a resistive implementation of the GP-SIMD architecture. In resistive GP-SIMD, a novel resistive row and column addressable $4F^{2}$ crossbar is utilized, replacing the modified CMOS $190F^{2}$ SRAM storage previously proposed for GP-SIMD architecture. The use of the resistive crossbar allows scaling the GP-SIMD from few millions to few hundred millions of processing units on a single silicon die. The performance, power consumption and power efficiency of a resistive GP-SIMD are compared with the CMOS version. We find that PiM architectures and, specifically, GP-SIMD benefit more than other many-core architectures from using resistive memory. A framework for in-place arithmetic operation on a single multivalued resistive cell is explored, demonstrating a potential to become a building block for next-generation PiM architectures.
Starting Page	1
Ending Page	22
Page Count	22
File Format	PDF
ISSN	15443566
e-ISSN	15443973
DOI	10.1145/2845084
Volume Number	12
Issue Number	4
Journal	ACM Transactions on Architecture and Code Optimization (TACO)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-01-06
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	GP-SIMD PIM SIMD In-memory computing Memristor Processing in memory Resistive RAM
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Information Systems Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

GP-SIMD Processing-in-Memory

Resistive Associative Processor

Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM

Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator

Multistate Register Based on Resistive RAM

A transpose-free in-place SIMD optimized FFT

Memristive devices in computing system: Promises and challenges

Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing

UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs

Resistive GP-SIMD Processing-In-Memory

Similar Documents

GP-SIMD Processing-in-Memory

Resistive Associative Processor

Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM

Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator

Multistate Register Based on Resistive RAM

A transpose-free in-place SIMD optimized FFT

Memristive devices in computing system: Promises and challenges

Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing

UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs

Resistive GP-SIMD Processing-In-Memory