NDLI: Future execution: A prefetching mechanism that uses multiple cores to speed up single threads

Please wait, while we are loading the content...

Future execution: A prefetching mechanism that uses multiple cores to speed up single threads

Content Provider	ACM Digital Library
Author	Ganusov, Ilya Burtscher, Martin
Copyright Year	2006
Abstract	This paper describes future execution (FE), a simple hardware-only technique to accelerate individual program threads running on multicore microprocessors. Our approach uses available idle cores to prefetch important data for the threads executing on the active cores. FE is based on the observation that many cache misses are caused by loads that execute repeatedly and whose address-generating program slices do not change (much) between consecutive executions. To exploit this property, FE dynamically creates a prefetching thread for each active core by simply sending a copy of all committed, register-writing instructions to an otherwise idle core. The key innovation is that on the way to the second core, a value predictor replaces each predictable instruction in the prefetching thread with a load immediate instruction, where the immediate is the predicted result that the instruction is likely to produce during its $\textit{n}th$ next dynamic execution. Executing this modified instruction stream (i.e., the prefetching thread) on another core allows to compute the future results of the instructions that are not directly predictable, issue prefetches into the shared memory hierarchy, and thus reduce the primary threads' memory access time. We demonstrate the viability and effectiveness of future execution by performing cycle-accurate simulations of a two-way CMP running the single-threaded SPECcpu2000 benchmark suite. Our mechanism improves program performance by 12%, on average, over a baseline that already includes an optimized hardware stream prefetcher. We further show that FE is complementary to runahead execution and that the combination of these two techniques raises the average speedup to 20% above the performance of the baseline processor with the aggressive stream prefetcher.
Starting Page	424
Ending Page	449
Page Count	26
File Format	PDF
ISSN	15443566
e-ISSN	15443973
DOI	10.1145/1187976.1187979
Volume Number	3
Issue Number	4
Journal	ACM Transactions on Architecture and Code Optimization (TACO)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-12-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Future execution Chip multiprocessors Memory wall Prefetching
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Information Systems Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems

Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors

Future execution: A prefetching mechanism that uses multiple cores to speed up single threads (2006)

Future execution: A prefetching mechanism that uses multiple cores to speed up single threads (2006)

Comparative evaluation of memory models for chip multiprocessors

Embedded RAIDs-on-chip for bus-based chip-multiprocessors

Rigel: A 1,024-Core Single-Chip Accelerator Architecture

Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs

The IBM Blue Gene/Q Compute Chip

Future execution: A prefetching mechanism that uses multiple cores to speed up single threads

Similar Documents

Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems

Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors

Future execution: A prefetching mechanism that uses multiple cores to speed up single threads (2006)

Future execution: A prefetching mechanism that uses multiple cores to speed up single threads (2006)

Comparative evaluation of memory models for chip multiprocessors

Embedded RAIDs-on-chip for bus-based chip-multiprocessors

Rigel: A 1,024-Core Single-Chip Accelerator Architecture

Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs

The IBM Blue Gene/Q Compute Chip

Future execution: A prefetching mechanism that uses multiple cores to speed up single threads