NDLI: Analytical Clustering Score with Application to Postplacement Register Clustering

Content Provider	ACM Digital Library
Author	Jiang, Iris Hui-Ru Li, Peixin Luo, Guojie Xu, Chang Shi, Yiyu
Copyright Year	2016
Abstract	Circuit clustering is usually done through discrete optimizations to enable circuit size reduction or design-specific cluster formation. In this article, we are interested in the register-clustering technique for clock-power reduction by leveraging new opportunities introduced by multibit flip-flop (MBFF). Currently, INTEGRA is the only existing postplacement MBFF clustering optimizer with a subquadratic time complexity. However, it severely degrades the wirelength, especially for realistic designs, which may nullify the benefits of MBFF clustering. In contrast, we formulate an analytical clustering score with a nonlinear programming framework, in which the wirelength objective can be seamlessly integrated and the solver has empirical subquadratic time complexity. With the MBFF library, the application of our analytical clustering method achieves comparable clock power to the state-of-the-art techniques, but further reduces the wirelength by about 25%. Even without the MBFF library, we can still achieve 30% clock wirelength reduction. In addition, the proposed method can potentially be integrated into an in-placement MBFF clustering solver and be applied to other problems that require formulating clustering scores in their objective functions.
Starting Page	1
Ending Page	18
Page Count	18
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/2894753
Volume Number	21
Issue Number	3
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-05-11
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Multibit flip-flops Clock power Placement Register clustering Timing
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving

Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization

Power-Driven Flip-Flop Merging and Relocation

Clock-Tree-Aware Incremental Timing-Driven Placement

Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging

Pulsed-Latch Aware Placement for Timing-Integrity Optimization

Timing analysis including clock skew

Postplacement voltage assignment under performance constraints

Postplacement rewiring by exhaustive search for functional symmetries

Analytical Clustering Score with Application to Postplacement Register Clustering

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