NDLI: General technology mapping for field-programmable gate arrays based on lookup tables

Content Provider	ACM Digital Library
Author	Hayes, John P. Chowdhary, Amit
Copyright Year	2002
Abstract	We present a general technology-mapping methodology (TULIP) for field-programmable gate arrays (FPGAs) that can yield optimal results, and is applicable to any FPGA with a logic block composed of lookup tables (LUTs). We introduce the concept of a virtual switch to model the internal connections of a logic block with multiple LUTs; each configuration of virtual switches is called a multiple-LUT block (MLB). A logic block can be precisely defined by a small but complete set of representative configurations called an MLB basis. The MLB bases for various commercial FPGA families are demonstrated. Given a logic block represented by its MLB basis, technology mapping is precisely formulated as a graph-covering problem, which is transformed into a mixed integer-linear programming (MILP) optimization problem in order to achieve our optimality and generality objectives. The MILP model is solved using a general-purpose MILP solver tool. The results of using TULIP for mapping some ISCAS-85 benchmark circuits to a variety of logic blocks are presented. Circuits of a few hundred gates can be mapped directly in a few minutes. To map larger circuits to complex logic blocks, some approximation techniques are proposed based on partitioning the input circuit and simplifying the MLB basis. We show that these approximations result in close-to-optimal mappings of the benchmark circuits.
Starting Page	1
Ending Page	32
Page Count	32
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/504914.504915
Volume Number	7
Issue Number	1
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2002-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Basis Circuit partitioning Field-programmable gate arrays Lookup tables (LUTs) Mapping Multiple-LUT blocks Nonrooted trees Rooted trees Synthesis
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Area-optimal technology mapping for field-programmable gate arrays based on lookup tables

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping

Improvements to Technology Mapping for LUT-Based FPGAs

Field programmable gate arrays (fpgas) • lookup tables (luts) • robust interconnect.

Technology mapping for field-programmable gate arrays using integer programming

Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate

Logic synthesis for field-programmable gate arrays

Optimality Study of Logic Synthesis for LUT-Based FPGAs

General technology mapping for field-programmable gate arrays based on lookup tables

Similar Documents

Area-optimal technology mapping for field-programmable gate arrays based on lookup tables

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping

Improvements to Technology Mapping for LUT-Based FPGAs

Field programmable gate arrays (fpgas) • lookup tables (luts) • robust interconnect.

Technology mapping for field-programmable gate arrays using integer programming

Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate

Logic synthesis for field-programmable gate arrays

Optimality Study of Logic Synthesis for LUT-Based FPGAs

General technology mapping for field-programmable gate arrays based on lookup tables