NDLI: Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures

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ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 13

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 12

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Dynamic Cache Pooling in 3D Multicore Processors

Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology

Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures

Process Variability and Electrostatic Analysis of Molecular QCA

Energy-Neutral Design Framework for Supercapacitor-Based Autonomous Wireless Sensor Networks

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Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures

Content Provider	ACM Digital Library
Author	Azghadi, Mostafa Rahimi Moradi, Saber Fasnacht, Daniel B Ozdas, Mehmet Sirin Indiveri, Giacomo
Copyright Year	2015
Description	Author Affiliation: University of Zurich, ETH Zurich, and University of Adelaide, Australia (Azghadi, Mostafa Rahimi); University of Zurich, ETH Zurich, Zurich, Switzerland (Moradi, Saber; Fasnacht, Daniel B; Ozdas, Mehmet Sirin; Indiveri, Giacomo)
Abstract	Hardware implementations of spiking neural networks offer promising solutions for computational tasks that require compact and low-power computing technologies. As these solutions depend on both the specific network architecture and the type of learning algorithm used, it is important to develop spiking neural network devices that offer the possibility to reconfigure their network topology and to implement different types of learning mechanisms. Here we present a neuromorphic multi-neuron VLSI device with on-chip programmable event-based hybrid analog/digital circuits; the event-based nature of the input/output signals allows the use of address-event representation infrastructures for configuring arbitrary network architectures, while the programmable synaptic efficacy circuits allow the implementation of different types of spike-based learning mechanisms. The main contributions of this article are to demonstrate how the programmable neuromorphic system proposed can be configured to implement specific spike-based synaptic plasticity rules and to depict how it can be utilised in a cognitive task. Specifically, we explore the implementation of different spike-timing plasticity learning rules online in a hybrid system comprising a workstation and when the neuromorphic VLSI device is interfaced to it, and we demonstrate how, after training, the VLSI device can perform as a standalone component (i.e., without requiring a computer), binary classification of correlated patterns.
Starting Page	1
Ending Page	18
Page Count	18
File Format	PDF
ISSN	15504832
e-ISSN	15504840
DOI	10.1145/2658998
Journal	ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number	12
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-09-02
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	AER STDP VLSI Asynchronous Emerging technologies Learning Neuromorphic Plasticity Realtime Subthreshold
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity

Neuromorphic Bistable VLSI Synapses with Spike-Timing-Dependent Plasticity (2002)

An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory

Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI

Analog VLSI Circuit Implementation of an Adaptive Neuromorphic Olfaction Chip

Spike-Timing-Dependent Plasticity With Weight Dependence Evoked From Physical Constraints

STDP and STDP Variations with Memristors for Spiking Neuromorphic Learning Systems

A hybrid analog/digital Spike-Timing Dependent Plasticity learning circuit for neuromorphic VLSI multi-neuron architectures

Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems

Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures

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