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Journal of The Institution of Engineers (India): Series B : Volume 98

Journal of The Institution of Engineers (India): Series B : Volume 97

Journal of The Institution of Engineers (India): Series B : Volume 97, Issue 4, December 2016

Journal of The Institution of Engineers (India): Series B : Volume 97, Issue 3, September 2016

A Novel Approach in Security Using Gyration Slab with Watermarking Technique

A Novel Hybrid Statistical Particle Swarm Optimization for Multimodal Functions and Frequency Control of Hybrid Wind-Solar System

An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

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Inspection–Repair based Availability Optimization of Distribution Systems using Teaching Learning based Optimization

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Journal of The Institution of Engineers (India): Series B : Volume 97, Issue 2, June 2016

Journal of The Institution of Engineers (India): Series B : Volume 97, Issue 1, March 2016

Journal of The Institution of Engineers (India): Series B : Volume 96

Journal of The Institution of Engineers (India): Series B : Volume 95

Journal of The Institution of Engineers (India): Series B : Volume 94

Journal of The Institution of Engineers (India): Series B : Volume 93

An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

Content Provider	Springer Nature Link
Author	Biswas, Baishik Chakrabarti, Indrajit Mukherjee, Rohan Saha, Priyabrata
Copyright Year	2015
Abstract	The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.
Starting Page	303
Ending Page	309
Page Count	7
File Format	PDF
ISSN	22502106
Journal	Journal of The Institution of Engineers (India): Series B
Volume Number	97
Issue Number	3
e-ISSN	22502114
Language	English
Publisher	Springer India
Publisher Date	2015-02-20
Publisher Place	New Delhi
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Motion estimation Enhanced Three Step Search FPGA Communications Engineering, Networks VLSI architecture
Content Type	Text
Resource Type	Article
Subject	Computer Science Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An efficient VLSI architecture for motion estimation using new three step search algorithm

High Performance VLSI Architecture for Three-Step Search Algorithm

An architecture for enhanced three step search generalized for hierarchical motion estimation algorithms

A New Hybrid Search Algorithm with Novel Cross-Diagonal-Hexagon Search Video Coding Algorithm for Block Motion Estimation

Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture

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An efficient vlsi-architecture for real-time motion estimation (1995).

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An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

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