NDLI: Statistical Drain Current and Input Capacitance of MOSFET Model for High Speed CMOS Circuits Application

Content Provider	Springer Nature Link
Author	Patil, Siddhasen R. Gautam, D. K.
Copyright Year	2015
Abstract	In this work, we propose for the first time statistical driving current and input capacitance model of MOSFET for high speed CMOS circuit applications. The proposed model is based on Berkeley Short-channel IGFET Model BSIM4v4.7. Rather than considering few parameters variations our algorithm considers all process parameters and environment parameters variations. The accuracy of the model was verified with Monte Carlo analysis for 32nm technology. The model shows better accuracy. The propagation delay of logic gates are calculated by using driving current and input capacitance of logic gates. Hence we proposed our MOSFET model to calculate the propagation delay of the logic gates. The validity of model is also verified for temperature and power supply variations. Finally, it is shown that the model can accurately predict the drain current and input capacitance of the MOSFET.
Starting Page	25
Ending Page	31
Page Count	7
File Format	PDF
ISSN	1876990X
Journal	Silicon
Volume Number	8
Issue Number	1
e-ISSN	18769918
Language	English
Publisher	Springer Netherlands
Publisher Date	2015-04-10
Publisher Place	Dordrecht
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Process parameters Environment parameters Inorganic Chemistry Materials Science Optics, Optoelectronics, Plasmonics and Optical Devices Environmental Chemistry
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials

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