NDLI: Design of 512-bit logic process-based single poly EEPROM IP

Content Provider	Springer Nature Link
Author	Jin, Li yan Jang, Ji Hye Yu, Yi ning Ha, Pan Bong Kim, Young Hee
Copyright Year	2011
Abstract	A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm$^{2}$, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18 μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 μW, respectively, and the EEPROM size is 0.12 mm$^{2}$.
Starting Page	2036
Ending Page	2044
Page Count	9
File Format	PDF
ISSN	10059784
Journal	Journal of Central South University of Technology
Volume Number	18
Issue Number	6
e-ISSN	19930666
Language	English
Publisher	Central South University
Publisher Date	2011-12-02
Publisher Place	Heidelberg
Access Restriction	Subscribed
Subject Keyword	single poly EEPROM cell Fowler-Nordheim tunneling logic process radio frequency identification small area Engineering Metallic Materials
Content Type	Text
Resource Type	Article
Subject	Mechanics of Materials Materials Science Mechanical Engineering

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Design of 512-bit logic process-based single poly EEPROM IP