NDLI: A system-level FPGA design methodology for video applications with weakly-programmable hardware components

Content Provider	Springer Nature Link
Author	Sahlbach, Henning Thiele, Daniel Ernst, Rolf
Copyright Year	2014
Abstract	High-performance video applications with real-time requirements play an important role in diverse application fields and are often executed by advanced parallel processors or GPUs. For embedded scenarios with strict energy constraints such as automotive image processing, FPGAs represent a feasible power-efficient computer platform. Unfortunately, their hardware-driven design concept results in long development cycles and impedes their acceptance in industrial practice. Additionally, the verification of the FPGA’s correctness and its performance figures are unavailable until a very late development stage, which is critical during design space exploration and the integration in complex embedded systems. Weakly-programmable architectures, supporting design and run-time reuse via flexible hardware components, represent a promising and efficient FPGA development approach. However, they currently lack suitable design and verification methodologies for real-time scenarios. Therefore, this paper proposes a system-level FPGA development concept for video applications with weakly-programmable hardware components. It combines rapid software prototyping with component-based FPGA design and advanced formal real-time analysis and code generation techniques. The presented approach enables an early verification of the application’s correctness, including exact performance figures. It provides a software-level verification of weakly-programmable hardware components and an automated assembly of the final hardware design. The developed tools and their usability are demonstrated by a binarization and a dense block matching application, which represents a basic preprocessing step in automotive image processing for driver assistance systems. When compared to a hand-optimized variant, the generated hardware design achieves comparable performance and chip area figures without requiring significant hardware integration effort.
Starting Page	291
Ending Page	309
Page Count	19
File Format	PDF
ISSN	18618200
Journal	Journal of Real-Time Image Processing
Volume Number	13
Issue Number	2
e-ISSN	18618219
Language	English
Publisher	Springer Berlin Heidelberg
Publisher Date	2014-03-07
Publisher Place	Berlin, Heidelberg
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FPGA Weakly-programmable Real-time image processing Formal timing analysis Dense block matching Image Processing and Computer Vision Multimedia Information Systems Computer Graphics Pattern Recognition Signal,Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Information Systems

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