NDLI: A single layer zero skew clock routing in X architecture

Content Provider	Springer Nature Link
Author	Shen, WeiXiang Cai, YiCi Hong, XianLong Hu, Jiang Lu, Bing
Copyright Year	2009
Abstract	With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture (called Planar-CRX). Our Planar-CRX method integrates the extended deferred-merge embedding algorithm (DME-X, which extends the DME algorithm to X architecture) with modified Ohtsuki’s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.
Starting Page	1466
Ending Page	1475
Page Count	10
File Format	PDF
ISSN	10092757
Journal	Science in China Series : Information Sciences
Volume Number	52
Issue Number	8
e-ISSN	18622836
Language	English
Publisher	SP Science in China Press
Publisher Date	2009-08-08
Publisher Place	Heidelberg
Access Restriction	Subscribed
Subject Keyword	clock routing single layer X architecture zero skew Information Systems and Communication Service
Content Type	Text
Resource Type	Article
Subject	Computer Science

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