NDLI: Improving multiprocessor performance with fine-grain coherence bypass

Content Provider	Springer Nature Link
Author	Wang, Hui Wang, Rui Luan, ZhongZhi Qian, XueHai Qian, DePei
Copyright Year	2014
Abstract	Efficient and scalable cache coherence protocol is crucial to high-performance servers with shared-memory. The directory-based cache coherence protocol is more desirable than the snooping-based protocol with respect to the scalability. However, even for the former protocol, scaling to a large number of cores is also challenging due to the additional area requirements of the directories. We observed that a significant percentage of the referenced memory blocks were only accessed by a single core (even in parallel applications) which could be considered as private memory blocks. An intuitive motivation from this observation is that memory blocks accessed by a single core do not require coherence maintenance. The issue is to identify the private block and track the change of its access pattern. We propose a novel hardware approach to (1) dynamically identify the shared memory blocks at the cache block level, and (2) bypass the coherence procedure for the private memory blocks. This approach increases the effectiveness of the directory-based approach and therefore improves the system performance. Experimental results showed that, our approach can on an average (1) avoid the coherence tracking of about 54% referenced memory blocks, (2) reduce the coherence overhead by 77%, (3) avoid 8% L2 cache misses, and (4) shorten the execution time of parallel applications by 13%.通过比较数据归属的内核ID区分共享和私有数据,并避免对私有数据进行一致性检验.可扩展的一致性协议是实现片上众核的关键因素之一.基于目录的一致性Cache受芯片面积约束,处理速度难以随核数扩展.通过实验发现,即便是并行程序,也只有少部分数据会同时被多个内核访问,而仅被单个内核访问的私有数据则不需要在目录中维护其一致性.本文通过在共享缓存中增加CoreID字段来区分共享和私有数据,并使一致性目录只维护共享数据的一致性,降低目录的存储开销和功耗等,同时提高系统性能.
Starting Page	1
Ending Page	15
Page Count	15
File Format	PDF
ISSN	1674733X
Journal	Science in China Series : Information Sciences
Volume Number	58
Issue Number	1
e-ISSN	18691919
Language	Chinese
Publisher	Science China Press
Publisher Date	2014-09-11
Publisher Place	Heidelberg
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	many-core cache coherence private memory block fine-grain coherence high performance Information Systems and Communication Service
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks

Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking

Improving multiprocessor performance with coarse-grain coherence tracking (2005)

The performance advantages of integrating block data transfer in cache-coherent multiprocessors (1996).

Improving multiprocessor performance with coarse-grain coherence tracking (2005)

Fine-grain producer-initiated communication in cache-coherent multiprocessors (1997).

Integrating Fine-Grained Message Passing In Cache Coherent Shared Memory Multiprocessors (1996)

SelectDirectory: A Selective Directory for Cache Coherence in Many-Core Architectures

Exploiting Cache Affinity in Software Cache Coherence (1994)

Improving multiprocessor performance with fine-grain coherence bypass

Similar Documents

Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks

Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking

Improving multiprocessor performance with coarse-grain coherence tracking (2005)

The performance advantages of integrating block data transfer in cache-coherent multiprocessors (1996).

Improving multiprocessor performance with coarse-grain coherence tracking (2005)

Fine-grain producer-initiated communication in cache-coherent multiprocessors (1997).

Integrating Fine-Grained Message Passing In Cache Coherent Shared Memory Multiprocessors (1996)

SelectDirectory: A Selective Directory for Cache Coherence in Many-Core Architectures

Exploiting Cache Affinity in Software Cache Coherence (1994)

Improving multiprocessor performance with fine-grain coherence bypass