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  1. Journal of Computer Science and Technology
  2. Journal of Computer Science and Technology : Volume 25
  3. Journal of Computer Science and Technology : Volume 25, Issue 2, March 2010
  4. Hierarchical Cache Directory for CMP
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Journal of Computer Science and Technology : Volume 32
Journal of Computer Science and Technology : Volume 31
Journal of Computer Science and Technology : Volume 30
Journal of Computer Science and Technology : Volume 29
Journal of Computer Science and Technology : Volume 28
Journal of Computer Science and Technology : Volume 27
Journal of Computer Science and Technology : Volume 26
Journal of Computer Science and Technology : Volume 25
Journal of Computer Science and Technology : Volume 25, Issue 6, November 2010
Journal of Computer Science and Technology : Volume 25, Issue 5, September 2010
Journal of Computer Science and Technology : Volume 25, Issue 4, July 2010
Journal of Computer Science and Technology : Volume 25, Issue 3, May 2010
Journal of Computer Science and Technology : Volume 25, Issue 2, March 2010
Preface
System Architecture of Godson-3 Multi-Core Processors
Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor
Research Progress of UniCore CPUs and PKUnity SoCs
YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP
Physical Design Methodology for Godson-2G Microprocessor
Managing Data-Objects in Dynamically Reconfigurable Caches
Hierarchical Cache Directory for CMP
CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors
Design and Application of Instruction Set Simulator on Multi-Core Verification
Location, Localization, and Localizability
ROAD+: Route Optimization with Additional Destination-Information and Its Mobility Management in Mobile Networks
Tree-Based Index Overlay in Hybrid Peer-to-Peer Systems
Location-Based Data Dissemination for Spatial Queries in Wireless Broadcast Environments
An Effective Semantic Cache for Exploiting XPath Query/View Answerability
A Multi-Key Pirate Decoder Against Traitor Tracing Schemes
Towards Risk Evaluation of Denial-of-Service Vulnerabilities in Security Protocols
Journal of Computer Science and Technology : Volume 25, Issue 1, January 2010
Journal of Computer Science and Technology : Volume 24
Journal of Computer Science and Technology : Volume 23
Journal of Computer Science and Technology : Volume 22
Journal of Computer Science and Technology : Volume 21
Journal of Computer Science and Technology : Volume 20
Journal of Computer Science and Technology : Volume 19
Journal of Computer Science and Technology : Volume 18
Journal of Computer Science and Technology : Volume 17
Journal of Computer Science and Technology : Volume 16
Journal of Computer Science and Technology : Volume 15
Journal of Computer Science and Technology : Volume 14
Journal of Computer Science and Technology : Volume 13
Journal of Computer Science and Technology : Volume 12

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Hierarchical Cache Directory for CMP

Content Provider Springer Nature Link
Author Guo, Song Liu Wang, Hai Xia Xue, Yi Bo Li, Chong Min Wang, Dong Sheng
Copyright Year 2010
Abstract As more processing cores are integrated into one chip and feature size continues to shrink, the average access latency for remote nodes using directory-based coherence protocol becomes higher, which greatly impacts system performance. Previous techniques such as data replication and data migration optimize the performance of the requesting core, but offer little improvement for neighbor nodes. Other techniques such as in-transit optimization try to reduce latency at the cost of increased storage. This paper introduces hierarchical cache directory into CMP (chip multiprocessor), which divides CMP tiles into multiple regions hierarchically, and combines it with data replication. A new directory organization is proposed to record the share status within a region and assist the regional home to complete operation efficiently. Simulation results show that for a 16-core CMP, compared to traditional directory, hierarchical cache directory reduces average access latency by 9% and on-chip network traffic by 34% on average with less storage. Theoretical analyses show that for a 2$^{n}$ × 2$^{n}$ tiled CMP, the average access latency in hierarchical cache directory asymptotically approaches a function that is independent of n, hence the architecture is highly scalable.
Starting Page 246
Ending Page 256
Page Count 11
File Format PDF
ISSN 10009000
Journal Journal of Computer Science and Technology
Volume Number 25
Issue Number 2
e-ISSN 18604749
Language English
Publisher Springer US
Publisher Date 2010-03-16
Publisher Place Boston
Access Restriction One Nation One Subscription (ONOS)
Subject Keyword cache coherence protocol hierarchical directory chip multiprocessor Information Systems Applications (incl.Internet) Artificial Intelligence (incl. Robotics) Data Structures, Cryptology and Information Theory Theory of Computation Software Engineering Computer Science
Content Type Text
Resource Type Article
Subject Theoretical Computer Science Computational Theory and Mathematics Computer Science Applications Software Hardware and Architecture
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