NDLI: A Test Approach for Look-Up Table Based FPGAs

Content Provider	Springer Nature Link
Author	Atoofian, Ehsan Navabi, Zainalabedin
Copyright Year	2006
Abstract	This paper describes a test architecture for minimum number of test configurations in test of FPGA (Field Programmable Gate Array) LUTs (Look Up Tables). The test architecture includes a TPG (Test Pattern Generator) that is tested while it is generating test data for LEs (Logic Elements) that form the CUT (Circuit Under Test). This scheme eliminates the need for switching LEs between CUT, TPG and ORA (Output Response Analyzer) and having to perform many more reconfigurations of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, a scheme is presented for testing other parts of LEs. Compared with other methods, the presented scheme uses the least number of reconfigurations of an FPGA for its LUT testing.
Starting Page	141
Ending Page	146
Page Count	6
File Format	PDF
ISSN	10009000
Journal	Journal of Computer Science and Technology
Volume Number	21
Issue Number	1
e-ISSN	18604749
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2006-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FPGA testing BIST LUT testing memory testing TPG with LE Theory of Computation Information Systems Applications (incl.Internet) Artificial Intelligence (incl. Robotics) Computer Science Software Engineering Data Structures, Cryptology and Information Theory
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Computer Science Applications Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Exploiting deterministic TPG for path delay testing

BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count

A hybrid model for smoke simulation

High level synthesis for loop-based BIST

A mixed-mode BIST scheme based on folding compression

Test Time Minimization for Hybrid BIST of Core-Based Systems

A Resource-Efficient Communication Architecture for Chip Multiprocessors on FPGAs

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement

Special announcement

A Test Approach for Look-Up Table Based FPGAs

Similar Documents

Exploiting deterministic TPG for path delay testing

BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count

A hybrid model for smoke simulation

High level synthesis for loop-based BIST

A mixed-mode BIST scheme based on folding compression

Test Time Minimization for Hybrid BIST of Core-Based Systems

A Resource-Efficient Communication Architecture for Chip Multiprocessors on FPGAs

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement

Special announcement

A Test Approach for Look-Up Table Based FPGAs