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| Content Provider | Springer Nature Link |
|---|---|
| Author | Lee, Edmund Lemieux, Guy Mirabbasi, Shahriar |
| Copyright Year | 2007 |
| Abstract | Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end multiplexing and driving logic, “finite” wire length, and a discrete number of repeaters. A metric introduced during the design is the “path delay profile”, or the arrival time of a signal at different points of a long wire. This method is used to design buffering strategies for interconnect based on 0.5, 2, and 3 mm wire lengths in 180 nm technology. These interconnect designs are coded into VPR along with an improved timing analyzer which accurately determines the “path delay profile” arrival times. Using VPR, average critical-path delay is reduced by 19% for 0.5 mm wires and by up to 46% for 3mm wires over previous designs. |
| Starting Page | 57 |
| Ending Page | 76 |
| Page Count | 20 |
| File Format | |
| ISSN | 19398018 |
| Journal | Journal of Signal Processing Systems |
| Volume Number | 51 |
| Issue Number | 1 |
| e-ISSN | 19398115 |
| Language | English |
| Publisher | Springer US |
| Publisher Date | 2007-10-04 |
| Publisher Place | Boston |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | FPGA FPGA interconnect interconnect design routing design computer-aided design Computer Imaging, Vision, Pattern Recognition and Graphics Pattern Recognition Image Processing and Computer Vision Electronic and Computer Engineering Circuits and Systems Signal, Image and Speech Processing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture |
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