NDLI: PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design

Content Provider	Springer Nature Link
Author	Wang, N. Sanusi, A. Zhao, P. Y. Elgamel, M. Bayoumi, M. A.
Copyright Year	2009
Abstract	With the de facto transformation of technology into nano-technology, more and more functional components can be embedded on a single silicon die, thus enabling high degree pipelining operations such as those required for multimedia applications. In recent years, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with multiple processors, on-chip memories, standard peripherals, and other functional blocks. The communication between these IP blocks is becoming the dominant critical system path and performance bottleneck of system-on-chip designs. Network-on-chip architectures, such as Virtual Channel (2004), Black-bus (2004), Pirate (2004), AEthereal (2005), and VICHAR (2006) architectures, emerged as promising solutions for future system-on-chip communication architecture designs. However, these existing architectures all suffer from certain problems, including high area cost and communication latency and/or low network throughput. This paper presents a novel network-on-chip architecture, Pipelining Multi-channel Central Caching, to address the shortcomings of the existing architectures. By embedding a central cache into every switch of the network, blocked head packets can be removed from the input buffers and stored in the caches temporally, thus alleviating the effect of head-of-line and deadlock problems and achieving higher network throughput and lower communication latency without paying the price of higher area cost. Experimental results showed that the proposed architecture exhibits both hardware simplicity and system performance improvement compared to the existing network-on-chip architectures.
Starting Page	315
Ending Page	331
Page Count	17
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	60
Issue Number	3
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2009-06-30
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	System-on-chip Network-on-chip On-chip communication architecture Multi-channel central caching Communication latency Throughput Computer Imaging, Vision, Pattern Recognition and Graphics Pattern Recognition Image Processing and Computer Vision Electrical Engineering Circuits and Systems Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

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PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design