NDLI: Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder

Content Provider	Springer Nature Link
Author	Pastuszak, Grzegorz Jakubowski, Mariusz
Copyright Year	2015
Abstract	The adaptive computationally-scalable motion estimation algorithm and its hardware implementation allow the H.264/AVC encoder to achieve efficiencies close to optimal in real-time conditions. Particularly, the search algorithm achieves results close to optimum even if the number of search points assigned to macroblocks is strongly limited and varies with time. The architecture implementing the algorithm developed and reported previously takes at least 674 clock cycles to interpolate and load reference area, and the number cannot be decreased without decreasing the search range. This paper proposes some optimizations of the architecture to increase the maximal throughput achieved by the motion estimation system even four times. Firstly, the chroma interpolation follows the search process, whereas the luma interpolation precedes it. Secondly, the luma interpolator computes 128 instead of 64 samples per each clock cycle. Thirdly, the number of on-chip memories keeping interpolated reference area is increased accordingly to 128. Fourthly, some modules previously working at the base frequency are redesigned to operate at the doubled clock. Since the on-chip memories do not store fractional-pel chroma samples, their joint size is reduced from 160.44 to 104.44 kB. Additional savings in the memory size are achieved by the sequential processing of two reference-picture areas for each macroblock. The architecture is verified in the real-time FPGA hardware encoder. Synthesis results show that the updated architecture can support 2160p@30fps encoding for 0.13 μm TSMC technology with a small increase in hardware resources and some losses in the compression efficiency. The efficiency is improved when processing smaller resolutions.
Starting Page	391
Ending Page	402
Page Count	12
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	82
Issue Number	3
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2015-07-21
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Video coding Motion estimation H.264/AVC FPGA Very large-scale integration (VLSI) Architecture design Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

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