NDLI: A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform

Content Provider	Springer Nature Link
Author	Wang, Haixin Bai, Guoqiang Chen, Hongyi
Copyright Year	2009
Abstract	This paper presents a high performance Network Security Processor (NSP) system architecture implementation intended for both Internet Protocol Security (IPSec) and Secure Socket Layer (SSL) protocol acceleration, which are widely employed in Virtual Private Network (VPN) and e-commerce applications. The efficient data transfer skeleton and optimized integration scheme of the parallel crypto engine arrays lead to a Gbps rate NSP, which is programmable with domain specific descriptor-based instructions for Gbps throughput IPSec and SSL applications. The descriptor-based control flow fragments large data packets and distributes them to the parallel crypto engine arrays, which fully utilizes the computation resources and improves the overall system data throughput. A prototyping platform for this NSP design is implemented with Xilinx XC3S5000 based FPGA chip set. Results show that the design gives a peak throughput for the IPSec ESP tunnel mode of 1.851 Gbps with over 1600 full SSL handshakes per second at a clock rate of 150 MHz.
Starting Page	311
Ending Page	324
Page Count	14
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	58
Issue Number	3
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2009-05-12
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Network security processor Cryptography Hardware implementation IPSec SSL/TLS Computer Imaging, Vision, Pattern Recognition and Graphics Pattern Recognition Image Processing and Computer Vision Electrical Engineering Circuits and Systems Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Efficient FPGA Implementation of a Programmable Architecture for GF(p) Elliptic Curve Crypto Computations

High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping

An Efficient FPGA-based Implementation of Fractional Fourier Transform Algorithm

Flexible and Expandable Speech Recognition Hardware with Weighted Finite State Transducers

High-Speed, SAD Based Wavefront Sensor Architecture Implementation on FPGA

3D EM/MPM Image Segmentation Using an FPGA Embedded Design Implementation

Hardware Implementation of FAST Algorithm for Mobile Applications

Parallel Memory Architecture for Elliptic Curve Cryptography over $$ \mathbb{G}\mathbb{F}{\left( p \right)} $$ Aimed at Efficient FPGA Implementation

FPGA architecture of the LDPS Motion Estimation for H.264/AVC Video Coding

A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform

Similar Documents

Efficient FPGA Implementation of a Programmable Architecture for GF(p) Elliptic Curve Crypto Computations

High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping

An Efficient FPGA-based Implementation of Fractional Fourier Transform Algorithm

Flexible and Expandable Speech Recognition Hardware with Weighted Finite State Transducers

High-Speed, SAD Based Wavefront Sensor Architecture Implementation on FPGA

3D EM/MPM Image Segmentation Using an FPGA Embedded Design Implementation

Hardware Implementation of FAST Algorithm for Mobile Applications

Parallel Memory Architecture for Elliptic Curve Cryptography over $$ \mathbb{G}\mathbb{F}{\left( p \right)} $$ Aimed at Efficient FPGA Implementation

FPGA architecture of the LDPS Motion Estimation for H.264/AVC Video Coding

A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform