NDLI: A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures

Content Provider	Springer Nature Link
Author	Barbieri, Iva Bariani, Massimo Cabitto, Alberto Raggio, Marco
Copyright Year	2005
Abstract	The increasing of computational power requirements for DSP and Multimedia application and the needs of easy-to-program development environment has driven recent programmable devices toward Very Long Instruction Word (VLIW) [1] architectures and Hw-Sw co-design environments [2]. VLIW architecture allows generating optimized machine code from high-level languages exploiting Instruction Level Parallelism (ILP) [3]. Furthermore, applications requirements and time to market constraints are growing dramatically moving functionalities toward System on Chip (SoC) direction. This paper presents VLIW-SIM, an Application-Driven Architecture-design approach based on Instruction Set simulation. VLIW architectures and Instruction Set simulation were chosen to fulfill multimedia domain requirements and to implement an efficient Hw-Sw co-design environment. The VLIW-SIM simulation technology is based on pipeline status modeling, Simulation cache and Simulation Oriented Hw description. An effective support for Hw-Sw co-design requires high simulation performance (in terms of Simulated Instruction per Second—SIPS), flexibility (the ability to represent a number of different architectures) and cycle accuracy. There is a strong trade-off between these features: cycle accurate or close to cycle accurate simulation have usually low performance [4, 5]. Good simulation performance can be obtained loosing the simulator flexibility. Moreover SoC simulation requires a further degree of flexibility in simulating different components (core, co-processors, memories, buses). The proposed approach is focused on interpretative (not compiled [6]) re-configurable Instruction Set Simulator (ISS) in order to support both application design and architecture exploration. VLIW-SIM main features are: efficient host resource allocation, Instruction Set and Architecture description Flexibility (Instruction Set Dynamic Generation and Simulation Oriented Hardware Description), Step by step pipeline status tracking, Simulation Speed and Accuracy. Performance of simulation test for three validation case studies (TI TMS320C62x, TI TMS320C64x and ST200) are reported.
Starting Page	153
Ending Page	168
Page Count	16
File Format	PDF
ISSN	09225773
Journal	Journal of Signal Processing Systems
Volume Number	41
Issue Number	2
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2005-09-01
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	architecture exploration VLIW DSP multimedia Hw-Sw co-design simulation ISA flexibility simulation speed simulation accuracy system on chip Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Signal Processing Information Systems Electrical and Electronic Engineering

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