NDLI: A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems

Content Provider	Springer Nature Link
Author	Guo, Yuanbin Cavallaro, Joseph R.
Copyright Year	2006
Abstract	In this paper, we propose a reduced complexity and power efficient System-on-Chip (SoC) architecture for adaptive interference suppression in CDMA systems. The adaptive Parallel-Residue-Compensation architecture leads to significant performance gain over the conventional interference cancellation algorithms. The multi-code commonality is explored to avoid the direct Interference Cancellation (IC), which reduces the IC complexity from $\mathcal{O}(K^2N)$ to $\mathcal{O}(KN)$ . The physical meaning of the complete versus weighted IC is applied to clip the weights above a certain threshold so as to reduce the VLSI circuit activity rate. Novel scalable SoC architectures based on simple combinational logic are proposed to eliminate dedicated multipliers with at least $10 \times$ saving in hardware resource. A Catapult C High Level Synthesis methodology is apply to explore the VLSI design space extensively and achieve at least $4 \times$ speedup. Multi-stage Convergence-Masking-Vector combined with clock gating is proposed to reduce the VLSI dynamic power consumption by up to $90 \%$
Starting Page	195
Ending Page	217
Page Count	23
File Format	PDF
ISSN	09225773
Journal	Journal of Signal Processing Systems
Volume Number	44
Issue Number	3
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2006-07-25
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	interference cancellation low power CDMA adaptive SoC VLSI Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Signal Processing Information Systems Electrical and Electronic Engineering

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