NDLI: Making DRAM refresh predictable

Content Provider	Springer Nature Link
Author	Bhat, Balasubramanya Mueller, Frank
Copyright Year	2011
Abstract	Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory can assure deadlines for a given task set when periods and worst-case execution times (WCETs) of tasks are known. While periods are generally derived from the problem specification, a task’s code needs to be statically analyzed to derive safe and tight bounds on its WCET. Such static timing analysis abstracts from program input and considers loop bounds and architectural features, such as pipelining and caching. However, unpredictability due to dynamic memory (DRAM) refresh cannot be accounted for by such analysis, which limits its applicability to systems with static memory (SRAM).In this paper, we assess the impact of DRAM refresh on task execution times and demonstrate how predictability is adversely affected leading to unsafe hard real-time system design. We subsequently contribute a novel and effective approach to overcome this problem through software-initiated DRAM refresh. We develop (1) a pure software and (2) a hybrid hardware/software refresh scheme. Both schemes provide predictable timings and fully replace the classical hardware auto-refresh. We discuss implementation details based on this design for multiple concrete embedded platforms and experimentally assess the benefits of different schemes on these platforms. We further formalize the integration of variable latency memory references into a data-flow framework suitable for static timing analysis to bound a task’s memory latencies with regard to their WCET. The resulting predictable execution behavior in the presence of DRAM refresh combined with the additional benefit of reduced access delays is unprecedented, to the best of our knowledge.
Starting Page	430
Ending Page	453
Page Count	24
File Format	PDF
ISSN	09226443
Journal	Real-Time Systems
Volume Number	47
Issue Number	5
e-ISSN	15731383
Language	English
Publisher	Springer US
Publisher Date	2011-05-12
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Real-time systems DRAM Worst-case execution time Timing analysis DRAM refresh Timing predictability Computer Systems Organization and Communication Networks Performance and Reliability Special Purpose and Application-Based Systems Communications Engineering, Networks Control, Robotics, Mechatronics
Content Type	Text
Resource Type	Article
Subject	Control and Optimization Computer Networks and Communications Control and Systems Engineering Electrical and Electronic Engineering Computer Science Applications Modeling and Simulation

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Making DRAM Refresh Predictable

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