NDLI: Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA

Content Provider	Springer Nature Link
Author	Kirubanandasarathy, N. Karthikeyan, K.
Copyright Year	2016
Abstract	In this paper, an area-efficient low power Fast Fourier Transform (FFT) processor is proposed for Multi Input Multi Output—Orthogonal Frequency Division Multiplexing (MIMO-OFDM) that consists of a modified architecture of radix-2 algorithm which is described as Radix-2 multipath delay commutation (R2MDC). Orthogonal frequency-division multiplexing is a popular method for high-data-rate wireless transmission. OFDM may be combined with multiple antennas at both the access point and mobile terminal to increase diversity gain and/or Enhance system capacity on a time-varying multi path fading channel, resulting in a multiple-input multiple-output OFDM system. This paper describes the design of R2MDC FFT for implementation of MIMO OFDM transceiver using FPGA targeted to future wireless LAN systems. The proposed system is pipeline Radix 2multipath delay commutation FFT has been designed for MIMO OFDM. The MIMO OFDM transceivers have been designed according to the proposed OFDM parameters. A low-power efficient and full-pipeline architecture enables the real-time operations of MIMO OFDM transceivers. The FPGA board has been developed to verify their circuit behavior and implementation of MIMO OFDM Transceivers.
Starting Page	465
Ending Page	471
Page Count	7
File Format	PDF
ISSN	10184864
Journal	Telecommunication Systems
Volume Number	63
Issue Number	3
e-ISSN	15729451
Language	English
Publisher	Springer US
Publisher Date	2016-01-12
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Radix-2 multipath delay commutation Frequency division multiplexing Multi input multi output—orthogonal frequency division multiplexing Inverse fast Fourier Transform Fast Fourier Transform Discrete Fourier Transform IT in Business Computer Communication Networks Artificial Intelligence (incl. Robotics) Probability Theory and Stochastic Processes
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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