NDLI: A chaotic encryption scheme for real-time embedded systems: design and implementation

Content Provider	Springer Nature Link
Author	Pande, Amit Zambre, Joseph
Copyright Year	2011
Abstract	Chaotic encryption schemes are believed to provide greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details over Xilinx Virtex-6 FPGA are provided. Logistic map is the simplest chaotic system and has high potential to be used to design a stream cipher for real-time embedded systems. Its simple construct and non-linear dynamics makes it a common choice for such applications. In this paper, we present a Modified Logistic Map (MLM) which improves the performance of Logistic Map in terms of higher Lyapunov exponent and uniformity of bifurcation map. It also avoids the stable orbits of logistic map giving a more chaotic behavior to the system. A stream cipher is built using MLM and random feedback scheme. The proposed cipher gives 16 bits of encrypted data per clock cycle. The hardware implementation results over Xilinx Virtex-6 FPGA give a synthesis clock frequency of 93 MHz and a throughput of 1.5 Gbps while using 16 hardware multipliers. This makes the cipher suitable for embedded devices which have tight constraints on power consumption, hardware resources and real-time parameters.
Starting Page	551
Ending Page	561
Page Count	11
File Format	PDF
ISSN	10184864
Journal	Telecommunication Systems
Volume Number	52
Issue Number	2
e-ISSN	15729451
Language	English
Publisher	Springer US
Publisher Date	2011-06-02
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Chaos Encryption Stream cipher FPGA implementation Business Information Systems Computer Communication Networks Artificial Intelligence (incl. Robotics) Probability Theory and Stochastic Processes
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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