NDLI: Capacity and interference modeling of CSMA/CA networks using SSI point processes

Content Provider	Springer Nature Link
Author	Busson, Anthony Chelius, Guillaume
Copyright Year	2013
Abstract	The relative location of simultaneous transmitters, i.e. the set of nodes transmitting a frame at a given time, has a crucial impact on the performance of multi hop wireless networks. Two fundamental aspects of wireless network performances are related to these locations: capacity and interference. Indeed, as interference results from the summation of signals stemmed by concurrent transmitters, it directly depends on the transmitters’ location. On the other hand, the network capacity is proportional to the number of simultaneous transmitters. In this paper, we investigate original point processes that can be used to model the location of transmitters that comply with the CSMA/CA policies, i.e. the Medium Access Control protocol used in 802.15.4 and 802.11 families of wireless technologies. We first propose the use of the Simple Sequential Inhibition point process to model CSMA/CA networks where clear channel assessment depends on the strongest emitter only. We then extend this point process to model a busy medium detection based on the strength of all concurrent signals. We finally compare the network capacity obtained through realistic simulations to a theoretical capacity estimated using the intensity of the SSI point process. It turns out that the proposed model is validated by the simulations.
Starting Page	25
Ending Page	39
Page Count	15
File Format	PDF
ISSN	10184864
Journal	Telecommunication Systems
Volume Number	57
Issue Number	1
e-ISSN	15729451
Language	English
Publisher	Springer US
Publisher Date	2013-07-31
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Multi hop wireless networks Network capacity Interference modeling SSI point process Business Information Systems Computer Communication Networks Artificial Intelligence (incl. Robotics) Probability Theory and Stochastic Processes
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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