NDLI: Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving

Content Provider	Springer Nature Link
Author	Chen, Ching Wen Chung, Chung Ping
Copyright Year	2005
Abstract	In fault-tolerant interconnection designs, many prior researches suggest good use of disjoint paths to improve the reliability of interconnection networks. Although disjoint paths increase reliability, they always cost the throughput penalty. To address the problems of both performance and fault-tolerant capability, the following issues should be carefully considered: (1) guarantee of at least two disjoint paths, (2) easy rerouting between disjoint paths, (3) keep low rerouting hops, (4) solve the occurrences of packets’ collision. In this paper, we consider these issues to design a fault-tolerant network called CSMIN (Combining Switches Multistage Interconnection Network). CSMIN provides two disjoint paths to guarantee one fault-tolerant and can dynamically reroute packets between these two paths to solve the collision situation. In other words, to switch packets between these two disjoint paths easily, CSMIN causes these two disjoint paths to have regular distances at each stage. Accordingly, a packet can be dynamically sent to the other disjoint path if it encounters a faulty or busy element. In addition, CSMIN presents low rerouting hops (an average of one rerouting hop) to maintain a low collision ratio. From the simulation result, CSMIN performs with a better arrival ratio than Gamma and other related disjoint paths networks do.
Starting Page	63
Ending Page	80
Page Count	18
File Format	PDF
ISSN	09208542
Journal	The Journal of Supercomputing
Volume Number	34
Issue Number	1
e-ISSN	15730484
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2005-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	multistage interconnection networks gamma interconnection networks disjoint paths dynamic rerouting rerouting hops collision ratio Computer Science Processor Architectures Programming Languages, Compilers, Interpreters
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection Networks

Designing a Fault-tolerant Fully-Chained Combining Switches Multi-stage Interconnection Network with Disjoint Paths

Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions

Multistage interconnection networks reliability analysis

Improved extra group network: a new fault-tolerant multistage interconnection network

Fault tolerance of hypercubes and folded hypercubes

Construction of vertex-disjoint paths in alternating group networks

Formulating broadcast reliability equations on multilayer multistage interconnection networks

Performance Analysis of Banyan-Type Multistage Interconnection Networks Under Nonuniform Traffic Pattern

Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving

Similar Documents

Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection Networks

Designing a Fault-tolerant Fully-Chained Combining Switches Multi-stage Interconnection Network with Disjoint Paths

Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions

Multistage interconnection networks reliability analysis

Improved extra group network: a new fault-tolerant multistage interconnection network

Fault tolerance of hypercubes and folded hypercubes

Construction of vertex-disjoint paths in alternating group networks

Formulating broadcast reliability equations on multilayer multistage interconnection networks

Performance Analysis of Banyan-Type Multistage Interconnection Networks Under Nonuniform Traffic Pattern

Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving