NDLI: A novel power-efficient multi-operand digit-multiplier using reconfiguration and clock gating

Content Provider	Springer Nature Link
Author	Elsayed, Essam El Boghdadi, Hatem M.
Copyright Year	2015
Abstract	Digit serial–serial multipliers are one approach to power-optimize multiplication where operands are fed one digit at a time. This significantly reduces the required chip area and hence reducing power. In this paper, a power-efficient reconfigurable digit serial–serial multiplier is proposed. Power efficiency is achieved using two techniques: reconfiguration and clock gating. Reconfiguration allows the proposed multiplier to perform multiplication of sub-width operands without extending to full width, that is, a multiplier composed of m sub-multipliers each of width n is capable of handling $$mn \times mn$$ , $$1/2mn \times 1/2mn$$ , $$1/4mn \times 1/4mn,\ldots , n \times n$$ multiplications. It also enables the multiplier to perform multiple multiplications concurrently rather than sequentially, that is, the multiplier is capable of handling $$1 \times ( mn \times mn)$$ , $$2\times (1/2mn \times 1/2), 4\times (1/4mn \times 1/4mn), \ldots , m\times (n\times n)$$ multiplications concurrently. Mathematical operations such as matrix product benefit most from concurrent multiplications. Clock gating is used to reduce power by disabling unused blocks and enabling utilized blocks only when their relevant inputs arrive. Compared with non-reconfigurable no-clock-gating design, simulation results show that the proposed multiplier reduces the power requirement. For $$m=2$$ , $$n=32$$ , and digit width $$d=4$$ power is reduced by 38 % for $$32\times 32$$ mode and by 49 % for $$2 \times (32 \times 32)$$ mode. Compared with standard parallel multiplier, simulation results also show that the proposed multiplier reduces energy requirement. For $$m=2, n=32$$ , and digit width $$d=32$$ , energy is reduced by 46 % for $$32 \times 32$$ mode and by 60 % for $$2 \times (32 \times 32)$$ mode.
Starting Page	2539
Ending Page	2564
Page Count	26
File Format	PDF
ISSN	09208542
Journal	The Journal of Supercomputing
Volume Number	71
Issue Number	7
e-ISSN	15730484
Language	English
Publisher	Springer US
Publisher Date	2015-04-03
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Digit serial–serial multiplier Reconfiguration Clock gating Power efficiency Programming Languages, Compilers, Interpreters Processor Architectures Computer Science
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Energy-efficient NoC with multi-granularity power optimization

Efficient Methods for Multi-Dimensional Array Redistribution

Design of a high-efficient MSD adder

Parallel reconfiguration algorithms for mesh-connected processor arrays

An energy and memory-efficient distributed self-reconfiguration for modular sensor/robot networks

The Multi-Level Communication: Efficient Routing for Interconnection Networks

Efficient Symbolic Analysis for Parallelizing Compilers and Performance Estimators

Software Architectures and Coordination Models

Efficient Collective Communications in Dual-Cube

A novel power-efficient multi-operand digit-multiplier using reconfiguration and clock gating

Similar Documents

Energy-efficient NoC with multi-granularity power optimization

Efficient Methods for Multi-Dimensional Array Redistribution

Design of a high-efficient MSD adder

Parallel reconfiguration algorithms for mesh-connected processor arrays

An energy and memory-efficient distributed self-reconfiguration for modular sensor/robot networks

The Multi-Level Communication: Efficient Routing for Interconnection Networks

Efficient Symbolic Analysis for Parallelizing Compilers and Performance Estimators

Software Architectures and Coordination Models

Efficient Collective Communications in Dual-Cube

A novel power-efficient multi-operand digit-multiplier using reconfiguration and clock gating