NDLI: Reversible logic based multiplication computing unit using binary tree data structure

Content Provider	Springer Nature Link
Author	Kotiyal, Saurabh Thapliyal, Himanshu Ranganathan, Nagarajan
Copyright Year	2015
Abstract	Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipationless computing and low-power computing, etc. In reversible logic there exists a one-to-one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Reversible circuits of many qubits are extremely difficult to realize; thus, reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature, researchers have proposed several designs of reversible multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and half adders for the addition of partial products increases the overhead in terms of the number of ancilla inputs and garbage outputs. This paper presents a binary tree-based design methodology for an $$N \times N$$ reversible multiplier. The proposed binary tree-based design methodology for $$N \times N$$ reversible multiplier performs the addition of partial products in parallel using the reversible ripple adders with zero ancilla bit and zero garbage bit; thereby, minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows a 17.86–60.34 % improvement in terms of ancilla inputs; and 21.43–52.17 % in terms of garbage outputs compared to all the existing reversible multiplier designs. The methodology is also extended to the design of $$N \times N$$ reversible signed multiplier based on modified Baugh–Wooley multiplication methodology.
Starting Page	2668
Ending Page	2693
Page Count	26
File Format	PDF
ISSN	09208542
Journal	The Journal of Supercomputing
Volume Number	71
Issue Number	7
e-ISSN	15730484
Language	English
Publisher	Springer US
Publisher Date	2015-03-25
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Reversible computing Arithmetic circuits Arithmetic logic unit (ALU) Baugh–Wooley multiplier Array multiplier Binary tree Programming Languages, Compilers, Interpreters Processor Architectures Computer Science
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Hardware and Architecture Software

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