NDLI: Multi-cache resizing via greedy coordinate descent

Content Provider	Springer Nature Link
Author	Choi, I. Stephen Yeung, Donald
Copyright Year	2016
Abstract	To reduce power consumption in CPUs, researchers have studied dynamic cache resizing. However, existing techniques only resize a single cache within a uniprocessor or the shared last-level cache (LLC) within a multi-core CPU. To maximize benefits, it is necessary to resize all caches, which in today’s CPUs includes one or two private caches per core and a shared LLC. Such multi-cache resizing (MCR) is challenging, because the multiple resizing decisions are coupled, yielding an enormous configuration space. In this paper, we present a dynamic MCR technique that uses search-based optimization. Our main contribution is a set of heuristics that enable the search to find the best configuration rapidly. In particular, our search moves in a coordinate descent (Manhattan) fashion across the configuration space. At each search step, we select the next cache for resizing greedily based on a power efficiency gain metric. To further enhance search speed, we permit parallel greedy selection. Across 60 multi-programmed workloads, our technique reduces power by 13.9% while sacrificing 1.5% of the performance.
Starting Page	2402
Ending Page	2429
Page Count	28
File Format	PDF
ISSN	09208542
Journal	The Journal of Supercomputing
Volume Number	73
Issue Number	6
e-ISSN	15730484
Language	English
Publisher	Springer US
Publisher Date	2016-12-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Cache resizing Multi-core CPUs Search-based optimization Power-efficient computing Programming Languages, Compilers, Interpreters Processor Architectures Computer Science
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Hardware and Architecture Software

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