NDLI: Cost-efficient design of a quantum multiplier

Content Provider	Springer Nature Link
Author	Babu, Hafiz Md. Hasan
Copyright Year	2016
Abstract	This paper proposes a cost-efficient quantum multiplier–accumulator unit. The paper also presents a fast multiplication algorithm and designs a novel quantum multiplier device based on the proposed algorithm with the optimum time complexity as multiplier is the major device of a multiplier–accumulator unit. We show that the proposed multiplication technique has time complexity $$O((3 {\hbox {log}}_{2}n)+1)$$ , whereas the best known existing technique has $$O(n{\hbox {log}}_{2} n)$$ , where n is the number of qubits. In addition, our design proposes three new quantum circuits: a circuit representing a quantum full-adder, a circuit known as quantum ANDing circuit, which performs the ANDing operation and a circuit presenting quantum accumulator. Moreover, the proposed quantum multiplier–accumulator unit is the first ever quantum multiplier–accumulator circuit in the literature till now, which has reduced garbage outputs and ancillary inputs to a great extent. The comparative study shows that the proposed quantum multiplier performs better than the existing multipliers in terms of depth, quantum gates, delays, area and power with the increasing number of qubits. Moreover, we design the proposed quantum multiplier–accumulator unit, which performs better than the existing ones in terms of hardware and delay complexities, e.g., the proposed ( $$n\times n$$ )—qubit quantum multiplier–accumulator unit requires $$O(n^{2})$$ hardware and $$O({\hbox {log}}_{2}n)$$ delay complexities, whereas the best known existing quantum multiplier–accumulator unit requires $$O(n^{3})$$ hardware and $$O((n-1)^{2} +1+n)$$ delay complexities. In addition, the proposed design achieves an improvement of 13.04, 60.08 and 27.2% for $$4\times 4$$ , 7.87, 51.8 and 27.1% for $$8\times 8$$ , 4.24, 52.14 and 27% for $$16\times 16$$ , 2.19, 52.15 and 27.26% for $$32 \times 32$$ and 0.78, 52.18 and 27.28% for $$128 \times 128$$ -qubit multiplications over the best known existing approach in terms of number of quantum gates, ancillary inputs and garbage outputs, respectively. Moreover, on average, the proposed design gains an improvement of 5.62% in terms of area and power consumptions over the best known existing approach.
Starting Page	1
Ending Page	38
Page Count	38
File Format	PDF
ISSN	15700755
Journal	Quantum Information Processing
Volume Number	16
Issue Number	1
e-ISSN	15731332
Language	English
Publisher	Springer US
Publisher Date	2016-12-21
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Controlled-V gate Qubits Quantum gate Quantum circuit Quantum Information Technology, Spintronics Quantum Computing Data Structures, Cryptology and Information Theory Quantum Physics Mathematical Physics
Content Type	Text
Resource Type	Article
Subject	Statistical and Nonlinear Physics Theoretical Computer Science Signal Processing Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering Modeling and Simulation

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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