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| Content Provider | Springer Nature Link |
|---|---|
| Author | Byrne, Rodrigue |
| Copyright Year | 1997 |
| Abstract | The aliasing probability (AP) of a Built-In Self-Test (BIST)architecture is the probability that an error response gets classified as agood response. A general technique to determine the AP for many common andalternative BIST response analysis (RA) architectures is presented here.This technique models the RA circuit as a Deterministic Finite Automaton(DFA), and determines the AP by counting the ratio of strings accepted bythe DFA to the total number of possible error strings. The strings acceptedby a DFA can be calculated by counting the paths in the DFA‘s statetransition graph (STG). Moreover, if the STG is complete, then theAP(k) = ((1/N)N$^{k}$-1)/(N$^{k}$-1), where k is the testlength and N is the number of states and input symbols. Thistechnique is demonstrated by determining the APs for the following RAarchitectures: Multiple-Input Shift Registers (MISRs), Cellular Automata(CA), Linear Feedback Shift Registers (LFSRs), accumulators, and a set ofalternative architectures directly based on DFAs. This paper also shows howthe adjacency matrix of the STG can be used to directly determine the AP ofany RA architecture modeled as a DFA. Finally, the eigenvalues andeigenvectors of the DFA‘s STG adjacency matrix are used to derive generalexpressions for the DFA‘s AP. |
| Starting Page | 263 |
| Ending Page | 272 |
| Page Count | 10 |
| File Format | |
| ISSN | 09238174 |
| Journal | Journal of Electronic Testing |
| Volume Number | 11 |
| Issue Number | 3 |
| e-ISSN | 15730727 |
| Language | English |
| Publisher | Kluwer Academic Publishers |
| Publisher Date | 1997-01-01 |
| Publisher Place | Boston |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Computer-Aided Engineering (CAD, CAE) and Design Electronic and Computer Engineering |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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