NDLI: Neural Network Guided Spatial Fault Resilience in Array Processors

Content Provider	Springer Nature Link
Author	Sindia, Suraj Agrawal, Vishwani D.
Copyright Year	2013
Abstract	Computing with large die-size graphical processors, that involves huge arrays of identical structures, in the late CMOS era is abounding with challenges due to spatial non-idealities arising from chip-to-chip and within-chip variation of MOSFET threshold voltage. In this paper, we propose a software-framework using machine learning for in-situ prediction and correction of computation corrupted due to threshold voltage variation of transistors. Semi-supervised training is imparted to a fully connected cascade feed-forward (FCCFF) neural network (NN). This FCCFF-NN then creates an accurate spatial map of faulty processing elements (PE), which are avoided in computing. Besides correcting spatial faults, any transient errors (such as single-event upsets) are also tracked and corrected if the number of affected PEs is large enough to cause noticeable computing errors. For experimental validation, we consider a 256 × 256 PE array. Each PE is comprised of add-accumulate-multiply (AAM) block with three 8-bit registers (two for inputs and a third for storing the computed result). One thousand instances of this processor array are created and PEs in each instance are randomly perturbed with threshold voltage variation. Common image processing operations such as low pass filtering and edge enhancement are performed on each of these 1,000 instances. A fraction of these images (about 10 %) is used to train the NN for spatial non-idealities. Based on this training, the NN is able to accurately predict the spatial extremities in 95 % of all the remaining 90 % of the cases. The proposed NN based error tolerance produces superior quality processed images whose degradation is no longer visually perceptible.
Starting Page	473
Ending Page	483
Page Count	11
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	29
Issue Number	4
e-ISSN	15730727
Language	English
Publisher	Springer US
Publisher Date	2013-07-25
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Array processors Fault resilience Neural network learning Process-variation faults Transient errors Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Soft Fault Classification of Analog Circuits Using Network Parameters and Neural Networks

Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

Model for Transient Fault Susceptibility of Combinational Circuits

Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits

Wavelet Neural Network Approach for Testing of Switched-Current Circuits

Adaptive Bayesian Diagnosis of Intermittent Faults

The Coupling Model for Function and Delay Faults

Modeling Feedback Bridging Faults with Non-Zero Resistance

Neural Network Guided Spatial Fault Resilience in Array Processors

Similar Documents

Soft Fault Classification of Analog Circuits Using Network Parameters and Neural Networks

Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

Model for Transient Fault Susceptibility of Combinational Circuits

Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits

Wavelet Neural Network Approach for Testing of Switched-Current Circuits

Adaptive Bayesian Diagnosis of Intermittent Faults

The Coupling Model for Function and Delay Faults

Modeling Feedback Bridging Faults with Non-Zero Resistance

Neural Network Guided Spatial Fault Resilience in Array Processors