NDLI: Access Port Protection for Reconfigurable Scan Networks

Content Provider	Springer Nature Link
Author	Barawski, Rafal Kochte, Michael A. Wunderlich, Hans Joachim
Copyright Year	2014
Abstract	Scan infrastructures based on IEEE Std. 1149.1 (JTAG), 1500 (SECT), and P1687 (IJTAG) provide a cost-effective access mechanism for test, reconfiguration, and debugging purposes. The improved accessibility of on-chip instruments, however, poses a serious threat to system safety and security. While state-of-the-art protection methods for scan architectures compliant with JTAG and SECT are very effective, most of these techniques face scalability issues in reconfigurable scan networks allowed by the upcoming IJTAG standard. This paper describes a scalable solution for multi-level access management in reconfigurable scan networks. The access to protected instruments is restricted locally at the interface to the network. The access restriction is realized by a sequence filter that allows only a precomputed set of scan-in access sequences. This approach does not require any modification of the scan architecture and causes no access time penalty. Therefore, it is well suited for core-based designs with hard macros and 3D integrated circuits. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of registers in the network.
Starting Page	711
Ending Page	723
Page Count	13
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	30
Issue Number	6
e-ISSN	15730727
Language	English
Publisher	Springer US
Publisher Date	2014-10-18
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Debug and diagnosis Reconfigurable scan network IJTAG IEEE P1687 Secure DFT Hardware security Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Securing Access to Reconfigurable Scan Networks

Fine-Grained Access Management in Reconfigurable Scan Networks

Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation

Scan pattern retargeting and merging with reduced access time

Modeling, verification and pattern generation for reconfigurable scan networks

Balanced Secure Scan: Partial Scan Approach for Secret Information Protection

Adaptive Debug and Diagnosis Without Fault Dictionaries

Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network

Accessing Embedded DfT Instruments with IEEE P1687

Access Port Protection for Reconfigurable Scan Networks

Similar Documents

Securing Access to Reconfigurable Scan Networks

Fine-Grained Access Management in Reconfigurable Scan Networks

Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation

Scan pattern retargeting and merging with reduced access time

Modeling, verification and pattern generation for reconfigurable scan networks

Balanced Secure Scan: Partial Scan Approach for Secret Information Protection

Adaptive Debug and Diagnosis Without Fault Dictionaries

Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network

Accessing Embedded DfT Instruments with IEEE P1687

Access Port Protection for Reconfigurable Scan Networks