NDLI: A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

Content Provider	Springer Nature Link
Author	Yuan, Haiying Guo, Kun Sun, Xun Ju, Zijian
Copyright Year	2016
Abstract	A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.
Starting Page	59
Ending Page	68
Page Count	10
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	32
Issue Number	1
e-ISSN	15730727
Language	English
Publisher	Springer US
Publisher Date	2016-01-19
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Don’t care bit filling Test data compression Test power dissipation Area overhead Alternating statistical run-length code Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering

Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead

Test Data Compression Using Multi-dimensional Pattern Run-length Codes

Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

Test Data Compression for System-on-a-Chip using Count Compatible Pattern Run-Length Coding

Test Data Compression Using Selective Sparse Storage

Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding

Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression

Double Hamming distance-based 2D reordering method for scan-in power reduction and test pattern compression

A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

Similar Documents

A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering

Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead

Test Data Compression Using Multi-dimensional Pattern Run-length Codes

Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

Test Data Compression for System-on-a-Chip using Count Compatible Pattern Run-Length Coding

Test Data Compression Using Selective Sparse Storage

Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding

Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression

Double Hamming distance-based 2D reordering method for scan-in power reduction and test pattern compression

A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding